diff options
| author | Sven Schnelle <svens@stackframe.org> | 2012-06-10 19:03:36 +0200 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2012-06-12 10:01:16 +0200 |
| commit | 0860e723cb40b82a9f7cc2652891499e0161d89e (patch) | |
| tree | e92d02c264411147a88fd2796c2f144da58d2afe /src | |
| parent | bb1c42b92037dc3dbbb639a1140dd284e978c595 (diff) | |
udelay: add missing bus frequency
commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency
detection on Sandybridge") reworked the udelay code, but didn't add
the 333MHz FSB entry used on Model 15 Xeons.
Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1099
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/x86/lapic/apic_timer.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index bb6cca7d9a..a4106d40f3 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -34,7 +34,7 @@ static int set_timer_fsb(void) { struct cpuinfo_x86 c; int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; - int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 }; + int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 }; get_fms(&c, cpuid_eax(1)); if (c.x86 != 6) @@ -45,7 +45,7 @@ static int set_timer_fsb(void) case 0x1c: /* Atom */ timer_fsb = core_fsb[rdmsr(0xcd).lo & 7]; break; - case 0xf: /* Core 2*/ + case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; break; |