sio1007: Properly build '.c' files

Properly build the super i/o .c files.  This prevents including
the .c file directly in romstage, which is generally bad practice.
Adding a Makefile and a .h file to include.

Change-Id: I0be66e94d3062a2c4a445cee2f12ec249598dc8b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4014
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

4 files changed, 53 insertions, 8 deletions

diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 363299df4b..f116668833 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -29,7 +29,7 @@
 #include <pc80/mc146818rtc.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include "superio/smsc/sio1007/early_serial.c"
+#include "superio/smsc/sio1007/chip.h"
 #include "northbridge/intel/sandybridge/sandybridge.h"
 #include "northbridge/intel/sandybridge/raminit.h"
 #include "southbridge/intel/bd82x6x/pch.h"
diff --git a/src/superio/smsc/sio1007/Makefile.inc b/src/superio/smsc/sio1007/Makefile.inc
new file mode 100644
index 0000000000..10684683f6
--- /dev/null
+++ b/src/superio/smsc/sio1007/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Sage Electronic Engineering LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+romstage-$(CONFIG_SUPERIO_SMSC_SIO1007) += early_serial.c
+
diff --git a/src/superio/smsc/sio1007/chip.h b/src/superio/smsc/sio1007/chip.h
new file mode 100644
index 0000000000..eee2811826
--- /dev/null
+++ b/src/superio/smsc/sio1007/chip.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_SMSC_1007_CHIP_H
+#define SUPERIO_SMSC_1007_CHIP_H
+
+void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask);
+int sio1007_enable_uart_at(u16 port);
+
+#endif
diff --git a/src/superio/smsc/sio1007/early_serial.c b/src/superio/smsc/sio1007/early_serial.c
index 859e351765..d1d28b2b11 100644
--- a/src/superio/smsc/sio1007/early_serial.c
+++ b/src/superio/smsc/sio1007/early_serial.c
@@ -17,13 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/*
- * The chip could be bootstrap mapped to one of four LPC addresses:
- * 0x2e, 0x4e, 0x162e, and 0x164e.
- */
-const u16 sio1007_lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e};
+#include <stdint.h>
+#include <arch/io.h>
+#include "chip.h"
 
-static void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask)
+void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask)
 {
 	u8 reg_value;
 
@@ -34,7 +32,7 @@ static void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask)
 	outb(reg_value, lpc_port + 1);
 }
 
-static int sio1007_enable_uart_at(u16 port)
+int sio1007_enable_uart_at(u16 port)
 {
 	/* Enable config mode. */
 	outb(0x55, port);