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authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-07-16 16:31:32 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-07-22 21:06:29 +0000
commit03ed5bff5cb13118b203b34b18e05694e713a30a (patch)
treee70d2b749b7c72b3c6936e0d755b6d8400be03d6 /src
parentbfd6521ce71b67a619da221dce7070db3959533b (diff)
soc/intel/cannonlake: Move tco_configure to bootblock
Similar to CB:43313 (SHA bb50c672278), it seems possible for the same problem to come up on cannonlake. Again, it should be harmless to configure the TCO device earlier in the boot flow. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib8883d27b2a0994a67ec5e044a692a2e853fd680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43538 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/cannonlake/bootblock/bootblock.c4
-rw-r--r--src/soc/intel/cannonlake/romstage/pch.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index de32fcda3d..a72b66e75f 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -3,6 +3,7 @@
#include <bootblock_common.h>
#include <cpu/x86/mtrr.h>
#include <intelblocks/gspi.h>
+#include <intelblocks/tco.h>
#include <intelblocks/uart.h>
#include <soc/bootblock.h>
#include <soc/iomap.h>
@@ -65,4 +66,7 @@ void bootblock_soc_init(void)
gpi_clear_int_cfg();
report_platform_info();
bootblock_pch_init();
+
+ /* Program TCO_BASE_ADDRESS and TCO Timer Halt */
+ tco_configure();
}
diff --git a/src/soc/intel/cannonlake/romstage/pch.c b/src/soc/intel/cannonlake/romstage/pch.c
index c85bdd667f..f94d611abe 100644
--- a/src/soc/intel/cannonlake/romstage/pch.c
+++ b/src/soc/intel/cannonlake/romstage/pch.c
@@ -1,14 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/smbus.h>
-#include <intelblocks/tco.h>
#include <soc/romstage.h>
void romstage_pch_init(void)
{
- /* Program TCO_BASE_ADDRESS and TCO Timer Halt */
- tco_configure();
-
/* Program SMBUS_BASE_ADDRESS and enable it */
smbus_common_init();
}