diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-25 12:58:32 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-04 22:03:03 +0000 |
| commit | f239b5a9f35faac861c8efd28d32c458e45cc890 (patch) | |
| tree | 5ad5f2f933b121588800659e82c1772bcc34fe05 /src | |
| parent | c5381e0f36b49356e965b9f82c5dbe66dc660a86 (diff) | |
nb/intel/haswell: Place CTDP ASL code in a separate scope
This is just to align the code with what Broadwell does.
Change-Id: I52fb1546d049ca9fa09d0c54304ca1d79f6c4c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46756
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/haswell/acpi/ctdp.asl | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/acpi/hostbridge.asl | 5 |
2 files changed, 6 insertions, 5 deletions
diff --git a/src/northbridge/intel/haswell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl index 7e59fb52ef..84c0f2f20a 100644 --- a/src/northbridge/intel/haswell/acpi/ctdp.asl +++ b/src/northbridge/intel/haswell/acpi/ctdp.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -//Scope (\_SB.PCI0.MCHC) -//{ +Scope (\_SB.PCI0.MCHC) +{ Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ Name (CTCC, 0) /* CTDP Current Selection */ Name (CTCN, 0) /* CTDP Nominal Select */ @@ -219,4 +219,4 @@ Release (CTCM) Return (1) } -//} +} diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index f36895d481..dc3a36fc95 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -80,8 +80,6 @@ Device (MCHC) Offset (0xbc), // Top of Low Used Memory TLUD, 32, } - - #include "ctdp.asl" } // Current Resource Settings @@ -227,3 +225,6 @@ Method (_CRS, 0, Serialized) Return (MCRS) } + +/* Configurable TDP */ +#include "ctdp.asl" |