soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK

Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build.  The .S files
are mostly duplicated code from the old cache_as_ram.inc file.

The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.

Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S.  Drop the BIST check like other devices.

Move InitReset and InitEarly to bootblock.  These AGESA entry
points set some default settings, and release/recapture the
AP cores.  There are currently some early dependencies on
InitReset.  Future work should include:
 * Pull the necessary functionality from InitReset into bootblock
 * Move InitReset and InitEarly to car_stage_entry() and out of
   bootblock
   - Add a mechanism for the BSP to give the APs an address
     to call and skip most of bootblock and verstage (when
     available) (1)
   - Reunify BiosCallOuts.c and OemCustomize.c

(1) During the InitReset call, the BSP enables the APs by setting
    core enable bits in F18F0x1DC and APs begin fetching/executing
    from the reset vector.  The BSP waits for all APs to also
    reach InitReset, where they enter an endless loop.  The BSP
    sends a command to them to execute a HLT instruction and the
    BSP eventually returns from InitReset.  The goal would be to
    preserve this process but prevent APs from rerunning early
    code.

Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>

20 files changed, 519 insertions, 488 deletions

diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c
index ac0ed6ad57..fd03f4e3fa 100644
--- a/src/mainboard/amd/gardenia/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c
@@ -13,83 +13,18 @@
  * GNU General Public License for more details.
  */
 
-#include <device/pci_def.h>
-#include <device/device.h>
 #include <AGESA.h>
-#include <amdlib.h>
 #include <BiosCallOuts.h>
-#include <Ids.h>
-#include <heapManager.h>
 #include <FchPlatform.h>
-#include <cbfs.h>
 #include <soc/imc.h>
 #include <soc/hudson.h>
 #include <stdlib.h>
-#include <dimmSpd.h>
-#include <agesawrapper.h>
 
-static AGESA_STATUS Fch_Oem_config(UINT32 Func,
-					UINTN FchData, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
-	{AGESA_ALLOCATE_BUFFER,          agesa_AllocateBuffer },
-	{AGESA_DEALLOCATE_BUFFER,        agesa_DeallocateBuffer },
-	{AGESA_LOCATE_BUFFER,            agesa_LocateBuffer },
-	{AGESA_READ_SPD,                 agesa_ReadSpd },
-	{AGESA_DO_RESET,                 agesa_Reset },
-	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
-	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_FCH_OEM_CALLOUT,          Fch_Oem_config },
-	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-static const GPIO_CONTROL oem_gardenia_gpio[] = {
-	/* BT radio disable */
-	{14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						| FCH_GPIO_OUTPUT_ENABLE},
-	/* NFC PU */
-	{64, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						| FCH_GPIO_OUTPUT_ENABLE},
-	/* NFC wake */
-	{65, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						| FCH_GPIO_OUTPUT_ENABLE},
-	/* Webcam */
-	{66, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						| FCH_GPIO_OUTPUT_ENABLE},
-	/* PCIe presence detect */
-	{69, Function0, FCH_GPIO_PULL_UP_ENABLE},
-	/* GPS sleep */
-	{70, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						| FCH_GPIO_OUTPUT_ENABLE},
-	/* MUX for Power Express Eval */
-	{116, Function1, FCH_GPIO_PULL_DOWN_ENABLE},
-	/* SD power */
-	{119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						 | FCH_GPIO_OUTPUT_ENABLE},
-	{-1}
-};
-/**
- * Fch Oem setting callback
- *
- *  Configure platform specific Hudson device,
- *   such as Azalia, SATA, IMC etc.
- */
-AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
+static AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
 {
 	AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
 
-	if (StdHeader->Func == AMD_INIT_RESET) {
-		FCH_RESET_DATA_BLOCK *FchParams_reset =
-					(FCH_RESET_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
-		FchParams_reset->FchReset.SataEnable = hudson_sata_enable();
-		FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();
-		FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;
-	} else if (StdHeader->Func == AMD_INIT_ENV) {
+	if (StdHeader->Func == AMD_INIT_ENV) {
 		FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
 		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
 		if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
@@ -119,8 +54,25 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
 			FchParams_env->Sata.SataIdeMode = TRUE;
 			break;
 		}
+		printk(BIOS_DEBUG, "Done\n");
 	}
-	printk(BIOS_DEBUG, "Done\n");
 
 	return AGESA_SUCCESS;
 }
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
+	{AGESA_ALLOCATE_BUFFER,          agesa_AllocateBuffer },
+	{AGESA_DEALLOCATE_BUFFER,        agesa_DeallocateBuffer },
+	{AGESA_LOCATE_BUFFER,            agesa_LocateBuffer },
+	{AGESA_READ_SPD,                 agesa_ReadSpd },
+	{AGESA_DO_RESET,                 agesa_Reset },
+	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
+	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
+	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
+	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+	{AGESA_FCH_OEM_CALLOUT,          fch_initenv },
+	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
+};
+
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc
index ba5e3776fa..4c637bbfbf 100644
--- a/src/mainboard/amd/gardenia/Makefile.inc
+++ b/src/mainboard/amd/gardenia/Makefile.inc
@@ -13,6 +13,9 @@
 # GNU General Public License for more details.
 #
 
+bootblock-y += bootblock/BiosCallOuts.c
+bootblock-y += bootblock/OemCustomize.c
+
 romstage-y += BiosCallOuts.c
 romstage-y += OemCustomize.c
 
diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c
index 3a34761e50..3893e5dbcb 100644
--- a/src/mainboard/amd/gardenia/OemCustomize.c
+++ b/src/mainboard/amd/gardenia/OemCustomize.c
@@ -18,142 +18,6 @@
 
 #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
-/* Port descriptor list for Gardenia Rev. B */
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	/* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
-				2, 1,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x04, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 1),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
-				2, 2,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x17, 0)
-	},
-	/* Disable M.2 x1 on lane 1, D2F3 */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
-				2, 3,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x17, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
-				2, 4,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x13, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
-				2, 5,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x16, 0)
-	},
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	/* DDI0 - eDP */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
-	},
-	/* DDI1 - DP */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-	},
-	/* DDI2 - HDMI */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
-	},
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList
-};
-
-static const UINT32 AzaliaCodecAlc286Table[] = {
-	0x00172051, 0x001721C7, 0x00172222, 0x00172310,
-	0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00,
-	0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7,
-	0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40,
-	0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90,
-	0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41,
-	0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04,
-	0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41,
-	0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41,
-	0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40,
-	0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04,
-	0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04,
-	0x02050071, 0x02040014, 0x02050010, 0x02040C22,
-	0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50,
-	0x0205002D, 0x02041020, 0x02050020, 0x02040000,
-	0x02050019, 0x02040817, 0x02050035, 0x02041AA5,
-	0x02050063, 0x02042906, 0x02050063, 0x02042906,
-	0xffffffff
-};
-
-CONST CODEC_VERB_TABLE_LIST CodecTableList[] = {
-	{ (UINT32) 0x10ec0286, AzaliaCodecAlc286Table},
-	{ (UINT32) 0x0FFFFFFFF, (UINT32 *)0x0FFFFFFFF}
-};
-
-/*---------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the
- *    binary block interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      **PeiServices
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------*/
-VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->PlatformConfig.AzaliaCodecVerbTable =
-					(UINT64)(UINTN)CodecTableList;
-}
-
 static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
 	DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
 	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
new file mode 100644
index 0000000000..a54078a283
--- /dev/null
+++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <AGESA.h>
+#include <BiosCallOuts.h>
+#include <FchPlatform.h>
+#include <soc/hudson.h>
+#include <stdlib.h>
+
+static const GPIO_CONTROL oem_gardenia_gpio[] = {
+	/* BT radio disable */
+	{14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+	/* NFC PU */
+	{64, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+	/* NFC wake */
+	{65, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+	/* Webcam */
+	{66, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+	/* PCIe presence detect */
+	{69, Function0, FCH_GPIO_PULL_UP_ENABLE},
+	/* GPS sleep */
+	{70, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+	/* MUX for Power Express Eval */
+	{116, Function1, FCH_GPIO_PULL_DOWN_ENABLE},
+	/* SD power */
+	{119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						 | FCH_GPIO_OUTPUT_ENABLE},
+	{-1}
+};
+
+static AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
+{
+	AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
+
+	if (StdHeader->Func == AMD_INIT_RESET) {
+		FCH_RESET_DATA_BLOCK *FchParams_reset;
+		FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
+		printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+		FchParams_reset->FchReset.SataEnable = hudson_sata_enable();
+		FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();
+		FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;
+		printk(BIOS_DEBUG, "Done\n");
+	}
+
+	return AGESA_SUCCESS;
+}
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
+	{AGESA_FCH_OEM_CALLOUT,          fch_initreset },
+};
+
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
diff --git a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c
new file mode 100644
index 0000000000..5c16c39d6b
--- /dev/null
+++ b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <agesawrapper.h>
+#include <PlatformMemoryConfiguration.h>
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+
+/* Port descriptor list for Gardenia Rev. B */
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	/* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+				2, 1,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmL0sL1, 0x04, 0)
+	},
+	/* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 1),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+				2, 2,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmL0sL1, 0x17, 0)
+	},
+	/* Disable M.2 x1 on lane 1, D2F3 */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
+				2, 3,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmL0sL1, 0x17, 0)
+	},
+	/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+				2, 4,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmL0sL1, 0x13, 0)
+	},
+	/* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+				2, 5,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmL0sL1, 0x16, 0)
+	},
+};
+
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	/* DDI0 - eDP */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
+	},
+	/* DDI1 - DP */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
+	},
+	/* DDI2 - HDMI */
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
+	},
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList
+};
+
+static const UINT32 AzaliaCodecAlc286Table[] = {
+	0x00172051, 0x001721C7, 0x00172222, 0x00172310,
+	0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00,
+	0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7,
+	0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40,
+	0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90,
+	0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41,
+	0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04,
+	0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41,
+	0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41,
+	0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40,
+	0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04,
+	0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04,
+	0x02050071, 0x02040014, 0x02050010, 0x02040C22,
+	0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50,
+	0x0205002D, 0x02041020, 0x02050020, 0x02040000,
+	0x02050019, 0x02040817, 0x02050035, 0x02041AA5,
+	0x02050063, 0x02042906, 0x02050063, 0x02042906,
+	0xffffffff
+};
+
+static CONST CODEC_VERB_TABLE_LIST CodecTableList[] = {
+	{ 0x10ec0286, AzaliaCodecAlc286Table},
+	{ 0x0FFFFFFFF, (void *)0x0FFFFFFFF}
+};
+
+/*---------------------------------------------------------------------------*/
+/**
+ *  OemCustomizeInitEarly
+ *
+ *  Description:
+ *    This is the stub function will call the host environment through the
+ *    binary block interface (call-out port) to provide a user hook opportunity.
+ *
+ *  Parameters:
+ *    @param[in]      **PeiServices
+ *    @param[in]      *InitEarly
+ *
+ *    @retval         VOID
+ *
+ **/
+/*---------------------------------------------------------------------------*/
+VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->PlatformConfig.AzaliaCodecVerbTable =
+					(uint64_t)(uintptr_t)CodecTableList;
+}
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index 39422a10de..9a7f168f25 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -12,72 +12,3 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <cbmem.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/bist.h>
-#include <cpu/amd/car.h>
-#include <agesawrapper.h>
-#include <agesawrapper_call.h>
-#include <soc/hudson.h>
-#include <amdblocks/psp.h>
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	u32 val;
-
-	amd_initmmio();
-	hudson_lpc_port80();
-	hudson_lpc_decode();
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x30);
-
-		if (IS_ENABLED(CONFIG_STONEYRIDGE_UART))
-			configure_hudson_uart();
-
-		post_code(0x31);
-		console_init();
-	}
-
-	/* Halt if there was a built in self test failure */
-	post_code(0x34);
-	/* Mask bit 31. One result of Silicon Observation */
-	report_bist_failure(bist & 0x7FFFFFFF);
-
-	/* Load MPB */
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
-
-	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
-
-	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
-
-	post_code(0x41);
-	psp_notify_dram();
-
-	post_code(0x42);
-	cbmem_initialize_empty();
-
-	post_code(0x43);
-	AGESAWRAPPER(amdinitenv);
-	/* TODO: Disable cache is not ok. */
-	disable_cache_as_ram();
-
-	post_code(0x50);
-	copy_and_run();
-
-	post_code(0x54);  /* Should never see this post code. */
-}
diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc
index 2a46284b4a..e11695bef3 100644
--- a/src/soc/amd/common/Makefile.inc
+++ b/src/soc/amd/common/Makefile.inc
@@ -1,6 +1,8 @@
 ifeq ($(CONFIG_SOC_AMD_COMMON),y)
 
-cpu_incs-y += $(src)/soc/amd/common/cache_as_ram.inc
+bootblock-y += agesawrapper.c
+bootblock-y += def_callouts.c
+bootblock-y += heapmanager.c
 
 romstage-y += agesawrapper.c
 romstage-y += def_callouts.c
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
new file mode 100644
index 0000000000..86cc77194c
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -0,0 +1,8 @@
+config SOC_AMD_COMMON_BLOCK_CAR
+	bool
+	default n
+	help
+	  This option allows the SOC to use a standard AMD cache-as-ram (CAR)
+	  implementation.  CAR setup is built into bootblock and teardown in
+	  romstage.  If it is not used the system must implement these functions
+	  separately.
diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc
new file mode 100644
index 0000000000..8e6972ed0a
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/Makefile.inc
@@ -0,0 +1,2 @@
+bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/cache_as_ram.S
+romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
new file mode 100644
index 0000000000..402da3acb6
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/******************************************************************************
+ * $Workfile:: cache_as_ram.S
+ *
+ * Description: CAR setup called from bootblock_crt0.S.
+ *
+ ******************************************************************************
+ */
+
+#include "gcccar.inc"
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+/*
+ * on entry:
+ *   mm0: BIST (ignored)
+ *   mm2_mm1: timestamp at bootblock_protected_mode_entry
+ */
+
+.global bootblock_pre_c_entry
+bootblock_pre_c_entry:
+
+	post_code(0xa0)
+
+	AMD_ENABLE_STACK
+
+	/* Align the stack and keep aligned for call to bootblock_c_entry() */
+	and	$0xfffffff0, %esp
+	sub	$8, %esp
+
+	movd	%mm2, %eax
+	pushl	%eax		/* tsc[63:32] */
+	movd	%mm1, %eax
+	pushl	%eax		/* tsc[31:0] */
+
+before_carstage:
+	post_code(0xa2)
+
+	call	bootblock_c_entry
+	/* Never reached */
+
+.halt_forever:
+	post_code(POST_DEAD_CODE)
+	hlt
+	jmp	.halt_forever
diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S
new file mode 100644
index 0000000000..ac36cb0e4f
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/car/exit_car.S
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <gcccar.inc>
+#include <cpu/x86/cache.h>
+
+.code32
+.globl chipset_teardown_car
+
+chipset_teardown_car:
+
+	/* Disable cache */
+	movl	%cr0, %eax
+	orl	$CR0_CacheDisable, %eax
+	movl	%eax, %cr0
+
+	AMD_DISABLE_STACK
+
+	/* enable cache */
+	movl	%cr0, %eax
+	andl	$(~(CR0_CD | CR0_NW)), %eax
+	movl	%eax, %cr0
+
+	ret
diff --git a/src/soc/amd/common/cache_as_ram.inc b/src/soc/amd/common/cache_as_ram.inc
deleted file mode 100644
index 7c8da8fa3e..0000000000
--- a/src/soc/amd/common/cache_as_ram.inc
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/******************************************************************************
- * AMD Generic Encapsulated Software Architecture
- *
- * $Workfile:: cache_as_ram.inc
- *
- * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
- *
- ******************************************************************************
- */
-
-#include "gcccar.inc"
-#include <cpu/x86/cache.h>
-
-/*
- * XMM map:
- *   xmm0: BIST
- *   xmm1: backup ebx -- cpu_init_detected
- */
-
-.code32
-.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
-
-cache_as_ram_setup:
-
-  post_code(0xa0)
-
-  /* enable SSE2 128bit instructions */
-  /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
-
-  movl %cr4, %eax
-  orl $(3<<9), %eax
-  movl %eax, %cr4
-
-  /* Get the cpu_init_detected */
-  mov $1, %eax
-  cpuid
-  shr $24, %ebx
-
-  /* Save the BIST result */
-  cvtsi2sd  %ebp, %xmm0
-
-  /* for normal part %ebx already contain cpu_init_detected from fallback call */
-
-  /* Save the cpu_init_detected */
-  cvtsi2sd  %ebx, %xmm1
-
-  post_code(0xa1)
-
-  AMD_ENABLE_STACK
-
-  /* Align the stack. */
-  and     $0xfffffff0, %esp
-
-#ifdef __x86_64__
-  /* switch to 64 bit long mode */
-  mov     %esi, %ecx
-  add     $0, %ecx # core number
-  xor     %eax, %eax
-  lea     (0x1000+0x23)(%ecx), %edi
-  mov     %edi, (%ecx)
-  mov     %eax, 4(%ecx)
-
-  lea     0x1000(%ecx), %edi
-  movl    $0x000000e3, 0x00(%edi)
-  movl    %eax, 0x04(%edi)
-  movl    $0x400000e3, 0x08(%edi)
-  movl    %eax, 0x0c(%edi)
-  movl    $0x800000e3, 0x10(%edi)
-  movl    %eax, 0x14(%edi)
-  movl    $0xc00000e3, 0x18(%edi)
-  movl    %eax, 0x1c(%edi)
-
-  # load ROM based identity mapped page tables
-  mov     %ecx, %eax
-  mov     %eax, %cr3
-
-  # enable PAE
-  mov     %cr4, %eax
-  bts     $5, %eax
-  mov     %eax, %cr4
-
-  # enable long mode
-  mov     $0xC0000080, %ecx
-  rdmsr
-  bts     $8, %eax
-  wrmsr
-
-  # enable paging
-  mov     %cr0, %eax
-  bts     $31, %eax
-  mov     %eax, %cr0
-
-  # use call far to switch to 64-bit code segment
-  ljmp $0x18, $1f
-1:
-  /* Pass the cpu_init_detected */
-  cvtsd2si        %xmm1, %esi
-
-  /* Pass the BIST result */
-  cvtsd2si        %xmm0, %edi
-
-
-  .code64
-  call    cache_as_ram_main
-  .code32
-
-#else
-
-  /* Restore the BIST result */
-  cvtsd2si  %xmm0, %edx
-
-  /* Restore the  cpu_init_detected */
-  cvtsd2si  %xmm1, %ebx
-
-  /* Must maintain 16-byte stack alignment here. */
-  pushl $0x0
-  pushl $0x0
-  pushl %ebx  /* init detected */
-  pushl %edx  /* bist */
-  call  cache_as_ram_main
-#endif
-
-  /* Should never see this postcode */
-  post_code(0xaf)
-stop:
-  jmp stop
-
-disable_cache_as_ram:
-  /* Save return stack */
-  movd 0(%esp), %xmm1
-  movd %esp, %xmm0
-
-  /* Disable cache */
-  movl	%cr0, %eax
-  orl	$CR0_CacheDisable, %eax
-  movl	%eax, %cr0
-
-  AMD_DISABLE_STACK
-
-  /* enable cache */
-  movl %cr0, %eax
-  andl $0x9fffffff, %eax
-  movl %eax, %cr0
-  xorl %eax, %eax
-
-  /* Restore the return stack */
-  wbinvd
-  movd %xmm0, %esp
-  movd %xmm1, (%esp)
-  ret
-
-cache_as_ram_setup_out:
-#ifdef __x86_64__
-.code64
-#endif
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 8d534cd6ac..aa694ef07b 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -40,10 +40,14 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_CONSTANT_RATE
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select TSC_SYNC_LFENCE
+	select COLLECT_TIMESTAMPS
 	select SOC_AMD_PI
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK
 	select SOC_AMD_COMMON_BLOCK_PSP
+	select SOC_AMD_COMMON_BLOCK_CAR
+	select C_ENVIRONMENT_BOOTBLOCK
+	select BOOTBLOCK_CONSOLE
 
 config UDELAY_LAPIC_FIXED_FSB
 	int
@@ -61,6 +65,14 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x10000
 
+config DCACHE_BSP_STACK_SIZE
+	depends on C_ENVIRONMENT_BOOTBLOCK
+	hex
+	default 0x4000
+	help
+	  The amount of anticipated stack usage in CAR by bootblock and
+	  other stages.
+
 config CPU_ADDR_BITS
 	int
 	default 48
@@ -124,10 +136,6 @@ config RAMBASE
 	hex
 	default 0x200000
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "soc/amd/stoneyridge/bootblock/bootblock.c"
-
 config SOUTHBRIDGE_AMD_STONEYRIDGE_SKIP_ISA_DMA_INIT
 	bool
 	default n
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 97d402e0a2..4997098267 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -37,6 +37,13 @@ subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/pae
 subdirs-y += ../../../cpu/x86/smm
 
+bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
+bootblock-y += fixme.c
+bootblock-y += bootblock/bootblock.c
+bootblock-y += early_setup.c
+bootblock-y += tsc_freq.c
+
+romstage-y += romstage.c
 romstage-y += early_setup.c
 romstage-y += dimmSpd.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 8efe744384..473b118d11 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -1,7 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Intel Corporation..
+ * Copyright (C) 2017 Advanced Micro Devices
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,52 +15,49 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
-#include <device/pci_ids.h>
-#include <soc/pci_devs.h>
+#include <console/console.h>
+#include <smp/node.h>
+#include <bootblock_common.h>
+#include <agesawrapper.h>
+#include <agesawrapper_call.h>
+#include <soc/hudson.h>
 
-/*
- * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
- *
- * Hardware should enable LPC ROM by pin straps. This function does not
- * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
- *
- * The HUDSON power-on default is to map 512K ROM space.
- *
- */
-static void hudson_enable_rom(void)
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
-	u8 reg8;
-	pci_devfn_t dev;
+	/*
+	 * Call lib/bootblock.c main with BSP, shortcut for APs
+	 *  todo: rearchitect AGESA entry points to remove need
+	 *        to run amdinitreset, amdinitearly from bootblock.
+	 *        Remove AP shortcut.
+	 */
+	if (!boot_cpu())
+		bootblock_soc_early_init(); /* APs will not return */
 
-	dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
+	bootblock_main_with_timestamp(base_timestamp);
+}
 
-	/* Decode variable LPC ROM address ranges 1 and 2. */
-	reg8 = pci_io_read_config8(dev, 0x48);
-	reg8 |= (1 << 3) | (1 << 4);
-	pci_io_write_config8(dev, 0x48, reg8);
+void bootblock_soc_early_init(void)
+{
+	amd_initmmio();
 
-	/* LPC ROM address range 1: */
-	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
-	pci_io_write_config16(dev, 0x68, 0x000e);
-	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
-	pci_io_write_config16(dev, 0x6a, 0x000f);
+	if (!boot_cpu())
+		bootblock_soc_init(); /* APs will not return */
 
-	/* LPC ROM address range 2: */
-	/*
-	 * Enable LPC ROM range start at:
-	 * 0xfff8(0000): 512KB
-	 * 0xfff0(0000): 1MB
-	 * 0xffe0(0000): 2MB
-	 * 0xffc0(0000): 4MB
-	 */
-	pci_io_write_config16(dev, 0x6c, 0x10000
-					- (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
-	/* Enable LPC ROM range end at 0xffff(ffff). */
-	pci_io_write_config16(dev, 0x6e, 0xffff);
+	bootblock_fch_early_init();
+
+	post_code(0x90);
+	if (CONFIG_STONEYRIDGE_UART)
+		configure_hudson_uart();
 }
 
-static void bootblock_southbridge_init(void)
+void bootblock_soc_init(void)
 {
-	hudson_enable_rom();
+	u32 val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
+
+	post_code(0x37);
+	AGESAWRAPPER(amdinitreset);
+
+	post_code(0x38);
+	AGESAWRAPPER(amdinitearly); /* APs will not exit amdinitearly */
 }
diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c
index f1539eae52..c1a2978c0e 100644
--- a/src/soc/amd/stoneyridge/early_setup.c
+++ b/src/soc/amd/stoneyridge/early_setup.c
@@ -301,3 +301,51 @@ void hudson_tpm_decode_spi(void)
 	pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase
 							| ROUTE_TPM_2_SPI);
 }
+
+/*
+ * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
+ *
+ * Hardware should enable LPC ROM by pin straps. This function does not
+ * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
+ *
+ * The HUDSON power-on default is to map 512K ROM space.
+ *
+ */
+void hudson_enable_rom(void)
+{
+	u8 reg8;
+	pci_devfn_t dev;
+
+	dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
+
+	/* Decode variable LPC ROM address ranges 1 and 2. */
+	reg8 = pci_io_read_config8(dev, 0x48);
+	reg8 |= (1 << 3) | (1 << 4);
+	pci_io_write_config8(dev, 0x48, reg8);
+
+	/* LPC ROM address range 1: */
+	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
+	pci_io_write_config16(dev, 0x68, 0x000e);
+	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
+	pci_io_write_config16(dev, 0x6a, 0x000f);
+
+	/* LPC ROM address range 2: */
+	/*
+	 * Enable LPC ROM range start at:
+	 * 0xfff8(0000): 512KB
+	 * 0xfff0(0000): 1MB
+	 * 0xffe0(0000): 2MB
+	 * 0xffc0(0000): 4MB
+	 */
+	pci_io_write_config16(dev, 0x6c, 0x10000
+					- (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
+	/* Enable LPC ROM range end at 0xffff(ffff). */
+	pci_io_write_config16(dev, 0x6e, 0xffff);
+}
+
+void bootblock_fch_early_init(void)
+{
+	hudson_enable_rom();
+	hudson_lpc_port80();
+	hudson_lpc_decode();
+}
diff --git a/src/soc/amd/stoneyridge/include/soc/hudson.h b/src/soc/amd/stoneyridge/include/soc/hudson.h
index c69ab679e6..62d5a84395 100644
--- a/src/soc/amd/stoneyridge/include/soc/hudson.h
+++ b/src/soc/amd/stoneyridge/include/soc/hudson.h
@@ -179,6 +179,7 @@ static inline int hudson_ide_enable(void)
 					(CONFIG_STONEYRIDGE_SATA_MODE == 3);
 }
 
+void hudson_enable_rom(void);
 void configure_hudson_uart(void);
 void hudson_clk_output_48Mhz(void);
 void hudson_disable_4dw_burst(void);
@@ -201,5 +202,6 @@ void pm_write16(u8 reg, u16 value);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 void s3_resume_init_data(void *FchParams);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
+void bootblock_fch_early_init(void);
 
 #endif /* STONEYRIDGE_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index a87d66b845..e082a9d067 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -16,6 +16,7 @@
 #ifndef PI_STONEYRIDGE_NORTHBRIDGE_H
 #define PI_STONEYRIDGE_NORTHBRIDGE_H
 
+#include <arch/cpu.h>
 #include <arch/io.h>
 #include <device/device.h>
 
@@ -26,4 +27,7 @@ void domain_set_resources(device_t dev);
 void fam15_finalize(void *chip_info);
 void setup_uma_memory(void);
 
+/* todo: remove this when postcar stage is in place */
+asmlinkage void chipset_teardown_car(void);
+
 #endif /* PI_STONEYRIDGE_NORTHBRIDGE_H */
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
new file mode 100644
index 0000000000..1380fb7672
--- /dev/null
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <agesawrapper.h>
+#include <agesawrapper_call.h>
+#include <soc/northbridge.h>
+#include <soc/hudson.h>
+#include <amdblocks/psp.h>
+
+asmlinkage void car_stage_entry(void)
+{
+	console_init();
+
+	post_code(0x40);
+	AGESAWRAPPER(amdinitpost);
+
+	post_code(0x41);
+	psp_notify_dram();
+
+	post_code(0x42);
+	cbmem_initialize_empty();
+
+	/*
+	 * This writes contents to DRAM backing before teardown.
+	 * todo: move CAR teardown to postcar implementation and
+	 *       relocate amdinitenv to ramstage.
+	 */
+	chipset_teardown_car();
+
+	post_code(0x43);
+	AGESAWRAPPER(amdinitenv);
+
+	post_code(0x50);
+	run_ramstage();
+
+	post_code(0x54);  /* Should never see this post code. */
+}
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index cadccdc371..962f0fc0d2 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -146,6 +146,7 @@ $(obj)/agesa/libagesa.a: $(call src-to-obj,libagesa,$(agesa_src_files))
 	@printf "    AGESA      $(subst $(obj)/,,$(@))\n"
 	ar rcs $@ $+
 
+bootblock-libs += $(obj)/agesa/libagesa.a
 romstage-libs += $(obj)/agesa/libagesa.a
 ramstage-libs += $(obj)/agesa/libagesa.a