mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDs

Until now some FSP-S parameters were configured for Siemens APL
mainboards via the Binary Configuration Tool (BCT). For simplification,
the original APL FSP binary should now be used. For this purpose, the
corresponding FSP-S parameters are set via devicetree, respectively via
mainboard_silicon_init_params accordingly.

The following parameters are affected:
- Disable CPU power states (C-states)
- Set lowest Max Pkg Cstate - PkgC0C1
- Disable PCIe Hot Plug for all enabled RPs
- Disable PCIe Transmitter Half Swing for all RPs
- Disable PCIe Active State Power Management (ASPM) for all RPs
- Disable PCIe L1 Substates for all RPs

TEST:
- Compare old with new coreboot log on mc_apl5, found no differences
- Boot Linux v4.4 and check output of 'lspci'

Change-Id: I5af627defd6426140cc9a74bb18db400a8971d72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

7 files changed, 164 insertions, 86 deletions

diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c
index b2cd449b87..bca0cbb4c8 100644
--- a/src/mainboard/siemens/mc_apl1/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/mainboard.c
@@ -12,6 +12,7 @@
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/systemagent.h>
 #include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 #include <string.h>
 #include <timer.h>
 #include <timestamp.h>
@@ -173,6 +174,29 @@ static void config_pmic_imon(void)
 	printk(BIOS_DEBUG, "PMIC: Configure PMIC IMON - End\n");
 }
 
+void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
+{
+	printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__);
+
+	/* Disable CPU power states (C-states) */
+	silconfig->EnableCx = 0;
+
+	/* Set max Pkg Cstate to PkgC0C1 */
+	silconfig->PkgCStateLimit = 0;
+
+	/* Disable PCIe Transmitter Half Swing for all RPs */
+	memset(silconfig->PcieRpTransmitterHalfSwing, 0,
+			sizeof(silconfig->PcieRpTransmitterHalfSwing));
+
+	/* Disable PCI Express Active State Power Management for all RPs */
+	memset(silconfig->PcieRpAspm, 0,
+			sizeof(silconfig->PcieRpAspm));
+
+	/* Disable PCI Express L1 Substate for all RPs */
+	memset(silconfig->PcieRpL1Substates, 0,
+			sizeof(silconfig->PcieRpL1Substates));
+}
+
 static void mainboard_init(void *chip_info)
 {
 	const struct pad_config *pads;
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
index 2e43648dd7..92b4e7c1b8 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
@@ -6,14 +6,6 @@ chip soc/intel/apollolake
 
 	register "sci_irq" = "SCIS_IRQ10"
 
-	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
-	register "pcie_rp_clkreq_pin[1]" = "2" # FPGA
-	register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
-	register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
-	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
-
 	# EMMC TX DATA Delay 1
 	# Refer to EDS-Vol2-22.3.
 	# [14:8] steps of delay for HS400, each 125ps.
@@ -72,12 +64,28 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
-		device pci 13.0 on  end	# - RP 2 - PCIe A 0 - MACPHY
-		device pci 13.1 on  end	# - RP 3 - PCIe A 1 - MACPHY
-		device pci 13.2 off end	# - RP 4 - PCIe-A 2
-		device pci 13.3 off end	# - RP 5 - PCIe-A 3
-		device pci 14.0 on  end	# - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge
-		device pci 14.1 on  end	# - RP 1 - PCIe-B 1 - FPGA
+		device pci 13.0 on	# - RP 2 - PCIe A 0 - MACPHY
+			register "pcie_rp_clkreq_pin[2]" = "0"
+			register "pcie_rp_hotplug_enable[2]" = "0"
+		end
+		device pci 13.1 on	# - RP 3 - PCIe A 1 - MACPHY
+			register "pcie_rp_clkreq_pin[3]" = "1"
+			register "pcie_rp_hotplug_enable[3]" = "0"
+		end
+		device pci 13.2 off	# - RP 4 - PCIe-A 2
+			register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+		end
+		device pci 13.3 off	# - RP 5 - PCIe-A 3
+			register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+		end
+		device pci 14.0 on	# - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge
+			register "pcie_rp_clkreq_pin[0]" = "3"
+			register "pcie_rp_hotplug_enable[0]" = "0"
+		end
+		device pci 14.1 on	# - RP 1 - PCIe-B 1 - FPGA
+			register "pcie_rp_clkreq_pin[1]" = "2"
+			register "pcie_rp_hotplug_enable[1]" = "0"
+		end
 		device pci 15.0 on  end	# - XHCI
 		device pci 15.1 off end	# - XDCI
 		device pci 16.0 on	# - I2C 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
index 1ac551a373..047d9b11b9 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
@@ -6,15 +6,6 @@ chip soc/intel/apollolake
 
 	register "sci_irq" = "SCIS_IRQ10"
 
-	# Disable all clkreq of PCIe root ports as SMARC interface do not
-	# have this pins.
-	register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
-
 	# EMMC TX DATA Delay 1
 	# Refer to EDS-Vol2-22.3.
 	# [14:8] steps of delay for HS400, each 125ps.
@@ -64,12 +55,30 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
-		device pci 13.0 on  end	# - RP 2 - PCIe A 0
-		device pci 13.1 on  end	# - RP 3 - PCIe A 1
-		device pci 13.2 on  end	# - RP 4 - PCIe-A 2
-		device pci 13.3 on  end	# - RP 5 - PCIe-A 3
-		device pci 14.0 on  end	# - RP 0 - PCIe-B 0
-		device pci 14.1 on  end	# - RP 1 - PCIe-B 1
+		device pci 13.0 on	# - RP 2 - PCIe A 0
+			register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[2]" = "0"
+		end
+		device pci 13.1 on	# - RP 3 - PCIe A 1
+			register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[3]" = "0"
+		end
+		device pci 13.2 on	# - RP 4 - PCIe-A 2
+			register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[4]" = "0"
+		end
+		device pci 13.3 on	# - RP 5 - PCIe-A 3
+			register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[5]" = "0"
+		end
+		device pci 14.0 on	# - RP 0 - PCIe-B 0
+			register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[0]" = "0"
+		end
+		device pci 14.1 on	# - RP 1 - PCIe-B 1
+			register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[1]" = "0"
+		end
 		device pci 15.0 on  end	# - XHCI
 		device pci 15.1 off end	# - XDCI
 		device pci 16.0 on	# - I2C 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
index bc5a9cf6a7..66ff911a95 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
@@ -6,14 +6,6 @@ chip soc/intel/apollolake
 
 	register "sci_irq" = "SCIS_IRQ10"
 
-	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
-
 	# EMMC TX DATA Delay 1
 	# Refer to EDS-Vol2-22.3.
 	# [14:8] steps of delay for HS400, each 125ps.
@@ -60,12 +52,30 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
-		device pci 13.0 on  end	# - RP 2 - PCIe A 0
-		device pci 13.1 on  end	# - RP 3 - PCIe A 1
-		device pci 13.2 on  end	# - RP 4 - PCIe-A 2
-		device pci 13.3 on  end	# - RP 5 - PCIe-A 3
-		device pci 14.0 on  end	# - RP 0 - PCIe-B 0
-		device pci 14.1 on  end	# - RP 1 - PCIe-B 1
+		device pci 13.0 on	# - RP 2 - PCIe A 0
+			register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[2]" = "0"
+		end
+		device pci 13.1 on	# - RP 3 - PCIe A 1
+			register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[3]" = "0"
+		end
+		device pci 13.2 on	# - RP 4 - PCIe-A 2
+			register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[4]" = "0"
+		end
+		device pci 13.3 on	# - RP 5 - PCIe-A 3
+			register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[5]" = "0"
+		end
+		device pci 14.0 on	# - RP 0 - PCIe-B 0
+			register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[0]" = "0"
+		end
+		device pci 14.1 on	# - RP 1 - PCIe-B 1
+			register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[1]" = "0"
+		end
 		device pci 15.0 on  end	# - XHCI
 		device pci 15.1 off end	# - XDCI
 		device pci 16.0 on	# - I2C 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
index 7e5166650c..6f37848238 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
@@ -6,15 +6,6 @@ chip soc/intel/apollolake
 
 	register "sci_irq" = "SCIS_IRQ10"
 
-	# Disable all clkreq of PCIe root ports as SMARC interface do not
-	# have this pins.
-	register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
-
 	# EMMC TX DATA Delay 1
 	# Refer to EDS-Vol2-22.3.
 	# [14:8] steps of delay for HS400, each 125ps.
@@ -61,12 +52,30 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
-		device pci 13.0 on  end	# - RP 2 - PCIe A 0
-		device pci 13.1 on  end	# - RP 3 - PCIe A 1
-		device pci 13.2 on  end	# - RP 4 - PCIe-A 2
-		device pci 13.3 on  end	# - RP 5 - PCIe-A 3
-		device pci 14.0 on  end	# - RP 0 - PCIe-B 0
-		device pci 14.1 on  end	# - RP 1 - PCIe-B 1
+		device pci 13.0 on	# - RP 2 - PCIe A 0
+			register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[2]" = "0"
+		end
+		device pci 13.1 on	# - RP 3 - PCIe A 1
+			register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[3]" = "0"
+		end
+		device pci 13.2 on	# - RP 4 - PCIe-A 2
+			register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[4]" = "0"
+		end
+		device pci 13.3 on	# - RP 5 - PCIe-A 3
+			register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[5]" = "0"
+		end
+		device pci 14.0 on	# - RP 0 - PCIe-B 0
+			register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[0]" = "0"
+		end
+		device pci 14.1 on	# - RP 1 - PCIe-B 1
+			register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[1]" = "0"
+		end
 		device pci 15.0 on  end	# - XHCI
 		device pci 15.1 off end	# - XDCI
 		device pci 16.0 on  end	# - I2C 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
index b5fb33b1a4..5d288c0c6b 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
@@ -6,14 +6,6 @@ chip soc/intel/apollolake
 
 	register "sci_irq" = "SCIS_IRQ10"
 
-	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp_clkreq_pin[0]" = "1"			# 14.0
-	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"	# 14.1
-	register "pcie_rp_clkreq_pin[2]" = "0"			# 13.0
-	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"	# 13.1
-	register "pcie_rp_clkreq_pin[4]" = "2"			# 13.2
-	register "pcie_rp_clkreq_pin[5]" = "3"			# 13.3
-
 	# EMMC TX DATA Delay 1
 	# Refer to EDS-Vol2-22.3.
 	# [14:8] steps of delay for HS400, each 125ps.
@@ -63,12 +55,28 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
-		device pci 13.0 on  end	# - RP 2 - PCIe A 0
-		device pci 13.1 off end	# - RP 3 - PCIe A 1
-		device pci 13.2 on  end	# - RP 4 - PCIe-A 2
-		device pci 13.3 on  end	# - RP 5 - PCIe-A 3
-		device pci 14.0 on  end	# - RP 0 - PCIe-B 0
-		device pci 14.1 off end	# - RP 1 - PCIe-B 1
+		device pci 13.0 on	# - RP 2 - PCIe A 0
+			register "pcie_rp_clkreq_pin[2]" = "0"
+			register "pcie_rp_hotplug_enable[2]" = "0"
+		end
+		device pci 13.1 off	# - RP 3 - PCIe A 1
+			register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+		end
+		device pci 13.2 on	# - RP 4 - PCIe-A 2
+			register "pcie_rp_clkreq_pin[4]" = "2"
+			register "pcie_rp_hotplug_enable[4]" = "0"
+		end
+		device pci 13.3 on	# - RP 5 - PCIe-A 3
+			register "pcie_rp_clkreq_pin[5]" = "3"
+			register "pcie_rp_hotplug_enable[5]" = "0"
+		end
+		device pci 14.0 on	# - RP 0 - PCIe-B 0
+			register "pcie_rp_clkreq_pin[0]" = "1"
+			register "pcie_rp_hotplug_enable[0]" = "0"
+		end
+		device pci 14.1 off	# - RP 1 - PCIe-B 1
+			register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+		end
 		device pci 15.0 on  end	# - XHCI
 		device pci 15.1 off end	# - XDCI
 		device pci 16.0 on	# - I2C 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
index 024f2c5e07..9c1054a9e7 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
@@ -6,14 +6,6 @@ chip soc/intel/apollolake
 
 	register "sci_irq" = "SCIS_IRQ10"
 
-	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
-
 	# 0:HS400(Default), 1:HS200, 2:DDR50
 	register "emmc_host_max_speed" = "1"
 
@@ -34,12 +26,30 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
-		device pci 13.0 on  end	# - RP 2 - PCIe A 0
-		device pci 13.1 on  end	# - RP 3 - PCIe A 1
-		device pci 13.2 on  end	# - RP 4 - PCIe-A 2
-		device pci 13.3 on  end	# - RP 5 - PCIe-A 3
-		device pci 14.0 on  end	# - RP 0 - PCIe-B 0
-		device pci 14.1 on  end	# - RP 1 - PCIe-B 1
+		device pci 13.0 on	# - RP 2 - PCIe A 0
+			register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[2]" = "0"
+		end
+		device pci 13.1 on	# - RP 3 - PCIe A 1
+			register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[3]" = "0"
+		end
+		device pci 13.2 on	# - RP 4 - PCIe-A 2
+			register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[4]" = "0"
+		end
+		device pci 13.3 on	# - RP 5 - PCIe-A 3
+			register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[5]" = "0"
+		end
+		device pci 14.0 on	# - RP 0 - PCIe-B 0
+			register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[0]" = "0"
+		end
+		device pci 14.1 on	# - RP 1 - PCIe-B 1
+			register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+			register "pcie_rp_hotplug_enable[1]" = "0"
+		end
 		device pci 15.0 on  end	# - XHCI
 		device pci 15.1 off end	# - XDCI
 		device pci 16.0 on	# - I2C 0