AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port

Move LPC decode enable out of agesawrapper.c. It should not be on the
execution path of AP CPUs and function is not related to AGESA per se.

Change-Id: I19d6a20fbc7a3d28601caa9aaa1d73d6930257ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7602
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)

12 files changed, 26 insertions, 46 deletions

diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c
index 22522db291..242aa27b2f 100644
--- a/src/mainboard/amd/olivehill/agesawrapper.c
+++ b/src/mainboard/amd/olivehill/agesawrapper.c
@@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 {
 	AGESA_STATUS                  Status;
 	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
 	AMD_CONFIG_PARAMS             StdHeader;
 
 	/*
@@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 	MsrReg = MsrReg | 0x0000400000000000;
 	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
 
-	/* For serial port */
-	PciData = 0xFF03FFD5;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 0a982b6fe8..1ff7a0b084 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -53,6 +53,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
 
+	/* Set LPC decode enables. */
+	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
+	pci_write_config32(dev, 0x44, 0xff03ffd5);
+
 	hudson_lpc_port80();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c
index c457fa3b5f..b4b39d0cd8 100644
--- a/src/mainboard/amd/parmer/agesawrapper.c
+++ b/src/mainboard/amd/parmer/agesawrapper.c
@@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 {
 	AGESA_STATUS                  Status;
 	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
 	AMD_CONFIG_PARAMS             StdHeader;
 
 	/*
@@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 	MsrReg = MsrReg | 0x0000400000000000;
 	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
 
-	/* For serial port */
-	PciData = 0xFF03FFD5;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 886ca57a00..17daa642e5 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -45,6 +45,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
 
+	/* Set LPC decode enables. */
+	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
+	pci_write_config32(dev, 0x44, 0xff03ffd5);
+
 	hudson_lpc_port80();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c
index cc3c0697bf..7425eacdde 100644
--- a/src/mainboard/amd/thatcher/agesawrapper.c
+++ b/src/mainboard/amd/thatcher/agesawrapper.c
@@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 {
 	AGESA_STATUS                  Status;
 	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
 	AMD_CONFIG_PARAMS             StdHeader;
 
 	/*
@@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 	MsrReg = MsrReg | 0x0000400000000000;
 	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
 
-	/* For serial port */
-	PciData = 0xFF03FFD5;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 0dee909937..f7a21ed643 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -46,13 +46,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 	u8 byte;
-	device_t dev;
+	pci_devfn_t dev;
+
 	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
 
+	/* Set LPC decode enables. */
+	dev = PCI_DEV(0, 0x14, 3);
+	pci_write_config32(dev, 0x44, 0xff03ffd5);
+
 	hudson_lpc_port80();
-	//__asm__ volatile ("1: jmp 1b");
-	/* TODO: */
-	dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
 	byte = pci_read_config8(dev, 0x48);
 	byte |= 3;		/* 2e, 2f */
 	pci_write_config8(dev, 0x48, byte);
diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c
index 62fc0531e0..1412392bc5 100644
--- a/src/mainboard/asrock/imb-a180/agesawrapper.c
+++ b/src/mainboard/asrock/imb-a180/agesawrapper.c
@@ -133,8 +133,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 {
 	AGESA_STATUS                  Status;
 	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
 	AMD_CONFIG_PARAMS             StdHeader;
 
 	/*
@@ -151,11 +149,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 	MsrReg = MsrReg | 0x0000400000000000;
 	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
 
-	/* For serial port */
-	PciData = 0xFF03FFD5;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 877d458b25..83155012e5 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -58,6 +58,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
 
+	/* Set LPC decode enables. */
+	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
+	pci_write_config32(dev, 0x44, 0xff03ffd5);
+
 	hudson_lpc_port80();
 
 	/* Enable the AcpiMmio space */
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c
index 5de359e89c..1ceffa049c 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c
@@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 {
 	AGESA_STATUS                  Status;
 	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
 	AMD_CONFIG_PARAMS             StdHeader;
 
 	/*
@@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 	MsrReg = MsrReg | 0x0000400000000000;
 	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
 
-	/* For serial port */
-	PciData = 0xFF03FFD5;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
index 5ae2c68731..086032dc73 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
@@ -41,6 +41,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
 
+	/* Set LPC decode enables. */
+	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
+	pci_write_config32(dev, 0x44, 0xff03ffd5);
+
 	hudson_lpc_port80();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/lenovo/g505s/agesawrapper.c b/src/mainboard/lenovo/g505s/agesawrapper.c
index 5de359e89c..1ceffa049c 100644
--- a/src/mainboard/lenovo/g505s/agesawrapper.c
+++ b/src/mainboard/lenovo/g505s/agesawrapper.c
@@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 {
 	AGESA_STATUS                  Status;
 	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
 	AMD_CONFIG_PARAMS             StdHeader;
 
 	/*
@@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 	MsrReg = MsrReg | 0x0000400000000000;
 	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
 
-	/* For serial port */
-	PciData = 0xFF03FFD5;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c
index 5ae2c68731..086032dc73 100644
--- a/src/mainboard/lenovo/g505s/romstage.c
+++ b/src/mainboard/lenovo/g505s/romstage.c
@@ -41,6 +41,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
 
+	/* Set LPC decode enables. */
+	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
+	pci_write_config32(dev, 0x44, 0xff03ffd5);
+
 	hudson_lpc_port80();
 
 	if (!cpu_init_detectedx && boot_cpu()) {