AMD Geode cpus: apply un-written naming rules

Kconfig directives to select chip drivers for compile literally
match the chip directory names capitalized and underscored.

Rename directories and Kconfig as follows:
   model_lx  -> geode_lx
   model_gx1 -> geode_gx1
   model_gx2 -> geode_gx2

Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/613
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

92 files changed, 137 insertions, 137 deletions

diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig
index 2f4ff33aec..dd78ca96e3 100644
--- a/src/cpu/amd/Kconfig
+++ b/src/cpu/amd/Kconfig
@@ -16,9 +16,9 @@ source src/cpu/amd/socket_S1G1/Kconfig
 
 source src/cpu/amd/model_fxx/Kconfig
 source src/cpu/amd/model_10xxx/Kconfig
-source src/cpu/amd/model_gx1/Kconfig
-source src/cpu/amd/model_gx2/Kconfig
-source src/cpu/amd/model_lx/Kconfig
+source src/cpu/amd/geode_gx1/Kconfig
+source src/cpu/amd/geode_gx2/Kconfig
+source src/cpu/amd/geode_lx/Kconfig
 
 source src/cpu/amd/sc520/Kconfig
 
diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc
index e695473e58..2ea376a2f8 100644
--- a/src/cpu/amd/Makefile.inc
+++ b/src/cpu/amd/Makefile.inc
@@ -8,9 +8,9 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2
 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3
 subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
 subdirs-$(CONFIG_CPU_AMD_SOCKET_C32) += socket_C32
-subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1
-subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2
-subdirs-$(CONFIG_CPU_AMD_LX) += model_lx
+subdirs-$(CONFIG_CPU_AMD_GEODE_GX1) += geode_gx1
+subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2
+subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
 subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
 
diff --git a/src/cpu/amd/model_gx1/Kconfig b/src/cpu/amd/geode_gx1/Kconfig
index c1c9b286a6..4a90c26d6e 100644
--- a/src/cpu/amd/model_gx1/Kconfig
+++ b/src/cpu/amd/geode_gx1/Kconfig
@@ -17,16 +17,17 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-config CPU_AMD_GX1
+config CPU_AMD_GEODE_GX1
 	bool
 
+if CPU_AMD_GEODE_GX1
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xc0000
-	depends on CPU_AMD_GX1
 
 config DCACHE_RAM_SIZE
 	hex
 	default 0x01000
-	depends on CPU_AMD_GX1
 
+endif # CPU_AMD_GEODE_GX1
diff --git a/src/cpu/amd/model_gx1/Makefile.inc b/src/cpu/amd/geode_gx1/Makefile.inc
index bf543a4665..d5bb1ef5ad 100644
--- a/src/cpu/amd/model_gx1/Makefile.inc
+++ b/src/cpu/amd/geode_gx1/Makefile.inc
@@ -22,7 +22,7 @@ subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
-driver-y += model_gx1_init.c
+driver-y += geode_gx1_init.c
 
-cpu_incs += $(src)/cpu/amd/model_gx1/cpu_setup.inc
-cpu_incs += $(src)/cpu/amd/model_gx1/gx_setup.inc
+cpu_incs += $(src)/cpu/amd/geode_gx1/cpu_setup.inc
+cpu_incs += $(src)/cpu/amd/geode_gx1/gx_setup.inc
diff --git a/src/cpu/amd/model_gx1/cpu_setup.inc b/src/cpu/amd/geode_gx1/cpu_setup.inc
index d701f8d226..d701f8d226 100644
--- a/src/cpu/amd/model_gx1/cpu_setup.inc
+++ b/src/cpu/amd/geode_gx1/cpu_setup.inc
diff --git a/src/cpu/amd/model_gx1/model_gx1_init.c b/src/cpu/amd/geode_gx1/geode_gx1_init.c
index e3c9034bee..60f9473470 100644
--- a/src/cpu/amd/model_gx1/model_gx1_init.c
+++ b/src/cpu/amd/geode_gx1/geode_gx1_init.c
@@ -73,7 +73,7 @@ unsigned long addr;
 }
 #endif
 
-static void model_gx1_init(device_t dev)
+static void geode_gx1_init(device_t dev)
 {
 #if 0
 	gx1_cpu_setup();
@@ -87,7 +87,7 @@ static void model_gx1_init(device_t dev)
 };
 
 static struct device_operations cpu_dev_ops = {
-	.init	= model_gx1_init,
+	.init	= geode_gx1_init,
 };
 
 static struct cpu_device_id cpu_table[] = {
diff --git a/src/cpu/amd/model_gx1/gx_setup.inc b/src/cpu/amd/geode_gx1/gx_setup.inc
index 6d0e289120..6d0e289120 100644
--- a/src/cpu/amd/model_gx1/gx_setup.inc
+++ b/src/cpu/amd/geode_gx1/gx_setup.inc
diff --git a/src/cpu/amd/model_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig
index 4515a71c37..0e25542582 100644
--- a/src/cpu/amd/model_gx2/Kconfig
+++ b/src/cpu/amd/geode_gx2/Kconfig
@@ -17,10 +17,10 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-config CPU_AMD_GX2
+config CPU_AMD_GEODE_GX2
 	bool
 
-if CPU_AMD_GX2
+if CPU_AMD_GEODE_GX2
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
@@ -55,5 +55,4 @@ config VSA_FILENAME
 	help
 	  The path and filename of the file to use as VSA.
 
-endif # CPU_AMD_GX2
-
+endif # CPU_AMD_GEODE_GX2
diff --git a/src/cpu/amd/model_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc
index 5e6d9ca366..b70537accf 100644
--- a/src/cpu/amd/model_gx2/Makefile.inc
+++ b/src/cpu/amd/geode_gx2/Makefile.inc
@@ -3,7 +3,7 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-driver-y += model_gx2_init.c
+driver-y += geode_gx2_init.c
 ramstage-y += cpubug.c
 
-cpu_incs += $(src)/cpu/amd/model_gx2/cache_as_ram.inc
+cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc
diff --git a/src/cpu/amd/model_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc
index 0af2fdf488..0af2fdf488 100644
--- a/src/cpu/amd/model_gx2/cache_as_ram.inc
+++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc
diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c
index 473766c8a4..473766c8a4 100644
--- a/src/cpu/amd/model_gx2/cpubug.c
+++ b/src/cpu/amd/geode_gx2/cpubug.c
diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/geode_gx2/cpureginit.c
index 0fc852d531..0fc852d531 100644
--- a/src/cpu/amd/model_gx2/cpureginit.c
+++ b/src/cpu/amd/geode_gx2/cpureginit.c
diff --git a/src/cpu/amd/model_gx2/model_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c
index 241c0f979f..7e481b5390 100644
--- a/src/cpu/amd/model_gx2/model_gx2_init.c
+++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c
@@ -16,9 +16,9 @@ static void vsm_end_post_smi(void)
 			  );
 }
 
-static void model_gx2_init(device_t dev)
+static void geode_gx2_init(device_t dev)
 {
-	printk(BIOS_DEBUG, "model_gx2_init\n");
+	printk(BIOS_DEBUG, "geode_gx2_init\n");
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
@@ -28,11 +28,11 @@ static void model_gx2_init(device_t dev)
 
 	vsm_end_post_smi();
 
-	printk(BIOS_DEBUG, "model_gx2_init DONE\n");
+	printk(BIOS_DEBUG, "geode_gx2_init DONE\n");
 };
 
 static struct device_operations cpu_dev_ops = {
-	.init	= model_gx2_init,
+	.init	= geode_gx2_init,
 };
 
 static struct cpu_device_id cpu_table[] = {
diff --git a/src/cpu/amd/model_gx2/syspreinit.c b/src/cpu/amd/geode_gx2/syspreinit.c
index 814034823c..814034823c 100644
--- a/src/cpu/amd/model_gx2/syspreinit.c
+++ b/src/cpu/amd/geode_gx2/syspreinit.c
diff --git a/src/cpu/amd/model_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig
index 742ef6911a..e5462c6edb 100644
--- a/src/cpu/amd/model_lx/Kconfig
+++ b/src/cpu/amd/geode_lx/Kconfig
@@ -1,7 +1,7 @@
-config CPU_AMD_LX
+config CPU_AMD_GEODE_LX
 	bool
 
-if CPU_AMD_LX
+if CPU_AMD_GEODE_LX
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
@@ -36,4 +36,4 @@ config VSA_FILENAME
 	help
 	  The path and filename of the file to use as VSA.
 
-endif # CPU_AMD_LX
+endif # CPU_AMD_GEODE_LX
diff --git a/src/cpu/amd/model_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc
index 3455d1e5d6..a5e12817eb 100644
--- a/src/cpu/amd/model_lx/Makefile.inc
+++ b/src/cpu/amd/geode_lx/Makefile.inc
@@ -3,7 +3,7 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 
-driver-y += model_lx_init.c
+driver-y += geode_lx_init.c
 ramstage-y += cpubug.c
 
-cpu_incs += $(src)/cpu/amd/model_lx/cache_as_ram.inc
+cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc
diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
index a1d775d6d6..a1d775d6d6 100644
--- a/src/cpu/amd/model_lx/cache_as_ram.inc
+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc
diff --git a/src/cpu/amd/model_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c
index e3b6e511ee..e3b6e511ee 100644
--- a/src/cpu/amd/model_lx/cpubug.c
+++ b/src/cpu/amd/geode_lx/cpubug.c
diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/geode_lx/cpureginit.c
index bad98b51bf..bad98b51bf 100644
--- a/src/cpu/amd/model_lx/cpureginit.c
+++ b/src/cpu/amd/geode_lx/cpureginit.c
diff --git a/src/cpu/amd/model_lx/model_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c
index 85e6bfbb27..bb9a73ecc0 100644
--- a/src/cpu/amd/model_lx/model_lx_init.c
+++ b/src/cpu/amd/geode_lx/geode_lx_init.c
@@ -38,9 +38,9 @@ static void vsm_end_post_smi(void)
 			  ".byte 0x0f, 0x38\n" "pop %ax\n");
 }
 
-static void model_lx_init(device_t dev)
+static void geode_lx_init(device_t dev)
 {
-	printk(BIOS_DEBUG, "model_lx_init\n");
+	printk(BIOS_DEBUG, "geode_lx_init\n");
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
@@ -56,11 +56,11 @@ static void model_lx_init(device_t dev)
 	outb(0x02, 0x92);
 	printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92));
 
-	printk(BIOS_DEBUG, "CPU model_lx_init DONE\n");
+	printk(BIOS_DEBUG, "CPU geode_lx_init DONE\n");
 };
 
 static struct device_operations cpu_dev_ops = {
-	.init = model_lx_init,
+	.init = geode_lx_init,
 };
 
 static struct cpu_device_id cpu_table[] = {
diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/geode_lx/msrinit.c
index 11182501c1..11182501c1 100644
--- a/src/cpu/amd/model_lx/msrinit.c
+++ b/src/cpu/amd/geode_lx/msrinit.c
diff --git a/src/cpu/amd/model_lx/syspreinit.c b/src/cpu/amd/geode_lx/syspreinit.c
index 35c54fba5f..35c54fba5f 100644
--- a/src/cpu/amd/model_lx/syspreinit.c
+++ b/src/cpu/amd/geode_lx/syspreinit.c
diff --git a/src/include/lib.h b/src/include/lib.h
index bbe735f89a..ea098874c5 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -41,7 +41,7 @@ int ram_check_nodie(unsigned long start, unsigned long stop);
 void quick_ram_check(void);
 
 /* Defined in romstage.c */
-#if CONFIG_CPU_AMD_LX
+#if CONFIG_CPU_AMD_GEODE_LX
 void cache_as_ram_main(void);
 #else
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
diff --git a/src/mainboard/aaeon/pfm-540i_revb/Kconfig b/src/mainboard/aaeon/pfm-540i_revb/Kconfig
index 3b31ffb3a5..9986987a37 100644
--- a/src/mainboard/aaeon/pfm-540i_revb/Kconfig
+++ b/src/mainboard/aaeon/pfm-540i_revb/Kconfig
@@ -3,7 +3,7 @@ if BOARD_AAEON_PFM_540I_REVB
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_SMSC_SMSCSUPERIO
diff --git a/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb b/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb
index b049160c6d..3987584d80 100644
--- a/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb
+++ b/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb
@@ -66,7 +66,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end
diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c
index b638a07427..4b510a9f21 100644
--- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c
+++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c
@@ -55,9 +55,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {
diff --git a/src/mainboard/advantech/pcm-5820/Kconfig b/src/mainboard/advantech/pcm-5820/Kconfig
index 7c87e28e3e..4e5c8f3b95 100644
--- a/src/mainboard/advantech/pcm-5820/Kconfig
+++ b/src/mainboard/advantech/pcm-5820/Kconfig
@@ -21,7 +21,7 @@ if BOARD_ADVANTECH_PCM_5820
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_WINBOND_W83977F
diff --git a/src/mainboard/advantech/pcm-5820/devicetree.cb b/src/mainboard/advantech/pcm-5820/devicetree.cb
index b416e9afce..b77fd06b49 100644
--- a/src/mainboard/advantech/pcm-5820/devicetree.cb
+++ b/src/mainboard/advantech/pcm-5820/devicetree.cb
@@ -51,6 +51,6 @@ chip northbridge/amd/gx1		# Northbridge
       register "ide1_enable" = "1"
     end
   end
-  chip cpu/amd/model_gx1		# CPU
+  chip cpu/amd/geode_gx1		# CPU
   end
 end
diff --git a/src/mainboard/amd/db800/Kconfig b/src/mainboard/amd/db800/Kconfig
index 834e08589c..ee2aa0f44c 100644
--- a/src/mainboard/amd/db800/Kconfig
+++ b/src/mainboard/amd/db800/Kconfig
@@ -3,7 +3,7 @@ if BOARD_AMD_DB800
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_WINBOND_W83627HF
diff --git a/src/mainboard/amd/db800/devicetree.cb b/src/mainboard/amd/db800/devicetree.cb
index e872571194..e0f20dc9b7 100644
--- a/src/mainboard/amd/db800/devicetree.cb
+++ b/src/mainboard/amd/db800/devicetree.cb
@@ -60,7 +60,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end
diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 264f1a809e..3590c37bfe 100644
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -49,9 +49,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {
diff --git a/src/mainboard/amd/norwich/Kconfig b/src/mainboard/amd/norwich/Kconfig
index b265eeb103..dec8e01d34 100644
--- a/src/mainboard/amd/norwich/Kconfig
+++ b/src/mainboard/amd/norwich/Kconfig
@@ -3,7 +3,7 @@ if BOARD_AMD_NORWICH
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/amd/norwich/devicetree.cb b/src/mainboard/amd/norwich/devicetree.cb
index 533ea92b2d..b2ede77ed1 100644
--- a/src/mainboard/amd/norwich/devicetree.cb
+++ b/src/mainboard/amd/norwich/devicetree.cb
@@ -33,7 +33,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end
diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index 097965f3b1..d8fca5a51f 100644
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -46,9 +46,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {
diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig
index 0477f32ec9..3f55d0135e 100644
--- a/src/mainboard/amd/rumba/Kconfig
+++ b/src/mainboard/amd/rumba/Kconfig
@@ -21,7 +21,7 @@ if BOARD_AMD_RUMBA
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX2
+	select CPU_AMD_GEODE_GX2
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5536
 	select UDELAY_TSC
diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb
index 40490e1875..e55f5c77b9 100644
--- a/src/mainboard/amd/rumba/devicetree.cb
+++ b/src/mainboard/amd/rumba/devicetree.cb
@@ -1,6 +1,6 @@
 chip northbridge/amd/gx2
 	device lapic_cluster 0 on
-		chip cpu/amd/model_gx2
+		chip cpu/amd/geode_gx2
 			device lapic 0 on end
 		end
 	end
diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index 49dfa68bd5..cec7c3698b 100644
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -26,9 +26,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/gx2/pll_reset.c"
 #include "northbridge/amd/gx2/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_gx2/cpureginit.c"
-#include "cpu/amd/model_gx2/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_gx2/cpureginit.c"
+#include "cpu/amd/geode_gx2/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {
diff --git a/src/mainboard/artecgroup/dbe61/Kconfig b/src/mainboard/artecgroup/dbe61/Kconfig
index 846000ccad..55c96ba4d3 100644
--- a/src/mainboard/artecgroup/dbe61/Kconfig
+++ b/src/mainboard/artecgroup/dbe61/Kconfig
@@ -3,7 +3,7 @@ if BOARD_ARTECGROUP_DBE61
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/artecgroup/dbe61/devicetree.cb b/src/mainboard/artecgroup/dbe61/devicetree.cb
index 4c2aab4748..c8110d16c1 100644
--- a/src/mainboard/artecgroup/dbe61/devicetree.cb
+++ b/src/mainboard/artecgroup/dbe61/devicetree.cb
@@ -33,7 +33,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index 83b59bbc53..f97af920c5 100644
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -61,9 +61,9 @@ static int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {
diff --git a/src/mainboard/asi/mb_5blgp/Kconfig b/src/mainboard/asi/mb_5blgp/Kconfig
index 5278369fd0..b4aa59f030 100644
--- a/src/mainboard/asi/mb_5blgp/Kconfig
+++ b/src/mainboard/asi/mb_5blgp/Kconfig
@@ -21,7 +21,7 @@ if BOARD_ASI_MB_5BLGP
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_NSC_PC87351
diff --git a/src/mainboard/asi/mb_5blgp/devicetree.cb b/src/mainboard/asi/mb_5blgp/devicetree.cb
index f50be6e70a..3ad1acb617 100644
--- a/src/mainboard/asi/mb_5blgp/devicetree.cb
+++ b/src/mainboard/asi/mb_5blgp/devicetree.cb
@@ -50,6 +50,6 @@ chip northbridge/amd/gx1		# Northbridge
       register "ide1_enable" = "0"	# No connector on this board
     end
   end
-  chip cpu/amd/model_gx1		# CPU
+  chip cpu/amd/geode_gx1		# CPU
   end
 end
diff --git a/src/mainboard/asi/mb_5blmp/Kconfig b/src/mainboard/asi/mb_5blmp/Kconfig
index 5b3b5bd4ce..8ce924e3c9 100644
--- a/src/mainboard/asi/mb_5blmp/Kconfig
+++ b/src/mainboard/asi/mb_5blmp/Kconfig
@@ -21,7 +21,7 @@ if BOARD_ASI_MB_5BLMP
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_NSC_PC87351
diff --git a/src/mainboard/asi/mb_5blmp/devicetree.cb b/src/mainboard/asi/mb_5blmp/devicetree.cb
index ded603a569..e3e0d95710 100644
--- a/src/mainboard/asi/mb_5blmp/devicetree.cb
+++ b/src/mainboard/asi/mb_5blmp/devicetree.cb
@@ -42,7 +42,7 @@ chip northbridge/amd/gx1		# Northbridge
       register "ide1_enable" = "1"
     end
   end
-  chip cpu/amd/model_gx1		# CPU
+  chip cpu/amd/geode_gx1		# CPU
   end
 end
 
diff --git a/src/mainboard/axus/tc320/Kconfig b/src/mainboard/axus/tc320/Kconfig
index dde2a364e7..fbe68e5f24 100644
--- a/src/mainboard/axus/tc320/Kconfig
+++ b/src/mainboard/axus/tc320/Kconfig
@@ -21,7 +21,7 @@ if BOARD_AXUS_TC320
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_NSC_PC97317
diff --git a/src/mainboard/axus/tc320/devicetree.cb b/src/mainboard/axus/tc320/devicetree.cb
index cf670c705a..3c17690d21 100644
--- a/src/mainboard/axus/tc320/devicetree.cb
+++ b/src/mainboard/axus/tc320/devicetree.cb
@@ -50,6 +50,6 @@ chip northbridge/amd/gx1		# Northbridge
       # register "ide1_enable" = "1"
     end
   end
-  chip cpu/amd/model_gx1		# CPU
+  chip cpu/amd/geode_gx1		# CPU
   end
 end
diff --git a/src/mainboard/bcom/winnet100/Kconfig b/src/mainboard/bcom/winnet100/Kconfig
index dbb2cb804c..5b74b4c22e 100644
--- a/src/mainboard/bcom/winnet100/Kconfig
+++ b/src/mainboard/bcom/winnet100/Kconfig
@@ -21,7 +21,7 @@ if BOARD_BCOM_WINNET100
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_NSC_PC97317
diff --git a/src/mainboard/bcom/winnet100/devicetree.cb b/src/mainboard/bcom/winnet100/devicetree.cb
index 872b8f389d..20c117e70e 100644
--- a/src/mainboard/bcom/winnet100/devicetree.cb
+++ b/src/mainboard/bcom/winnet100/devicetree.cb
@@ -51,6 +51,6 @@ chip northbridge/amd/gx1		# Northbridge
       register "ide1_enable" = "0"	# Not available/needed on this board
     end
   end
-  chip cpu/amd/model_gx1		# CPU
+  chip cpu/amd/geode_gx1		# CPU
   end
 end
diff --git a/src/mainboard/digitallogic/msm800sev/Kconfig b/src/mainboard/digitallogic/msm800sev/Kconfig
index 444023b2bd..0b54906757 100644
--- a/src/mainboard/digitallogic/msm800sev/Kconfig
+++ b/src/mainboard/digitallogic/msm800sev/Kconfig
@@ -3,7 +3,7 @@ if BOARD_DIGITALLOGIC_MSM800SEV
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_WINBOND_W83627HF
diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb
index c4dfa17970..e00b36f99f 100644
--- a/src/mainboard/digitallogic/msm800sev/devicetree.cb
+++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb
@@ -77,7 +77,7 @@ chip northbridge/amd/lx
 
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index 2f4cef1250..d30e2b0808 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -30,9 +30,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {
diff --git a/src/mainboard/eaglelion/5bcm/Kconfig b/src/mainboard/eaglelion/5bcm/Kconfig
index 65dd802bfe..f96c4941f3 100644
--- a/src/mainboard/eaglelion/5bcm/Kconfig
+++ b/src/mainboard/eaglelion/5bcm/Kconfig
@@ -21,7 +21,7 @@ if BOARD_EAGLELION_5BCM
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_NSC_PC97317
diff --git a/src/mainboard/eaglelion/5bcm/devicetree.cb b/src/mainboard/eaglelion/5bcm/devicetree.cb
index a08ffd4e3d..94e8fab6c0 100644
--- a/src/mainboard/eaglelion/5bcm/devicetree.cb
+++ b/src/mainboard/eaglelion/5bcm/devicetree.cb
@@ -45,7 +45,7 @@ chip northbridge/amd/gx1
     end
   end
 
-  chip cpu/amd/model_gx1
+  chip cpu/amd/geode_gx1
   end
 
 end
diff --git a/src/mainboard/iei/juki-511p/Kconfig b/src/mainboard/iei/juki-511p/Kconfig
index d948929a04..e44253f610 100644
--- a/src/mainboard/iei/juki-511p/Kconfig
+++ b/src/mainboard/iei/juki-511p/Kconfig
@@ -21,7 +21,7 @@ if BOARD_IEI_JUKI_511P
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_WINBOND_W83977F
diff --git a/src/mainboard/iei/juki-511p/devicetree.cb b/src/mainboard/iei/juki-511p/devicetree.cb
index be5f064b5c..8592c091db 100644
--- a/src/mainboard/iei/juki-511p/devicetree.cb
+++ b/src/mainboard/iei/juki-511p/devicetree.cb
@@ -50,7 +50,7 @@ chip northbridge/amd/gx1
     end
   end
 
-  chip cpu/amd/model_gx1
+  chip cpu/amd/geode_gx1
   end
 
 end
diff --git a/src/mainboard/iei/nova4899r/Kconfig b/src/mainboard/iei/nova4899r/Kconfig
index 3cc5ddb04b..a829796794 100644
--- a/src/mainboard/iei/nova4899r/Kconfig
+++ b/src/mainboard/iei/nova4899r/Kconfig
@@ -21,7 +21,7 @@ if BOARD_IEI_NOVA_4899R
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_WINBOND_W83977TF
diff --git a/src/mainboard/iei/nova4899r/devicetree.cb b/src/mainboard/iei/nova4899r/devicetree.cb
index e6a0c8000a..8055fb1e68 100644
--- a/src/mainboard/iei/nova4899r/devicetree.cb
+++ b/src/mainboard/iei/nova4899r/devicetree.cb
@@ -57,7 +57,7 @@ chip northbridge/amd/gx1
     end
   end
 
-  chip cpu/amd/model_gx1
+  chip cpu/amd/geode_gx1
   end
 
 end
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
index e393609c88..eae72aef4d 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
+++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
@@ -3,7 +3,7 @@ if BOARD_IEI_PCISA_LX_800_R10
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_WINBOND_W83627HF
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
index a7e74d0442..2d37ecf438 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
+++ b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
@@ -68,7 +68,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index 4121e3e91d..aec984327a 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -53,9 +53,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {
diff --git a/src/mainboard/lippert/frontrunner/Kconfig b/src/mainboard/lippert/frontrunner/Kconfig
index 4e8cee0d18..ba1d5f14d9 100644
--- a/src/mainboard/lippert/frontrunner/Kconfig
+++ b/src/mainboard/lippert/frontrunner/Kconfig
@@ -3,7 +3,7 @@ if BOARD_LIPPERT_FRONTRUNNER
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX2
+	select CPU_AMD_GEODE_GX2
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5535
 	select HAVE_DEBUG_SMBUS
diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb
index fa7c6e73a7..63ac140136 100644
--- a/src/mainboard/lippert/frontrunner/devicetree.cb
+++ b/src/mainboard/lippert/frontrunner/devicetree.cb
@@ -1,6 +1,6 @@
 chip northbridge/amd/gx2
   device lapic_cluster 0 on
-    chip cpu/amd/model_gx2
+    chip cpu/amd/geode_gx2
       device lapic 0 on end
     end
   end
diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c
index 97172505ed..bdbf059d4c 100644
--- a/src/mainboard/lippert/frontrunner/romstage.c
+++ b/src/mainboard/lippert/frontrunner/romstage.c
@@ -66,9 +66,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/gx2/pll_reset.c"
 #include "northbridge/amd/gx2/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_gx2/cpureginit.c"
-#include "cpu/amd/model_gx2/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_gx2/cpureginit.c"
+#include "cpu/amd/geode_gx2/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {
diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig
index 9b20aa0759..118809d333 100644
--- a/src/mainboard/lippert/hurricane-lx/Kconfig
+++ b/src/mainboard/lippert/hurricane-lx/Kconfig
@@ -3,7 +3,7 @@ if BOARD_LIPPERT_HURRICANE_LX
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_ITE_IT8712F
diff --git a/src/mainboard/lippert/hurricane-lx/devicetree.cb b/src/mainboard/lippert/hurricane-lx/devicetree.cb
index 17c0b8b659..5aa4cd4dd6 100644
--- a/src/mainboard/lippert/hurricane-lx/devicetree.cb
+++ b/src/mainboard/lippert/hurricane-lx/devicetree.cb
@@ -83,7 +83,7 @@ chip northbridge/amd/lx
   end
   # APIC cluster is late CPU init.
   device lapic_cluster 0 on
-    chip cpu/amd/model_lx
+    chip cpu/amd/geode_lx
       device lapic 0 on end
     end
   end
diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index fe007310ae..29aa9d1e4f 100644
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -77,9 +77,9 @@ static int smc_send_config(unsigned char config_data)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 static const u16 sio_init_table[] = { // hi=data, lo=index
 	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)
diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig
index 7b45d36ea1..12a3ae145b 100644
--- a/src/mainboard/lippert/literunner-lx/Kconfig
+++ b/src/mainboard/lippert/literunner-lx/Kconfig
@@ -3,7 +3,7 @@ if BOARD_LIPPERT_LITERUNNER_LX
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_ITE_IT8712F
diff --git a/src/mainboard/lippert/literunner-lx/devicetree.cb b/src/mainboard/lippert/literunner-lx/devicetree.cb
index 44d6010d35..b14247121c 100644
--- a/src/mainboard/lippert/literunner-lx/devicetree.cb
+++ b/src/mainboard/lippert/literunner-lx/devicetree.cb
@@ -80,7 +80,7 @@ chip northbridge/amd/lx
   end
   # APIC cluster is late CPU init.
   device lapic_cluster 0 on
-    chip cpu/amd/model_lx
+    chip cpu/amd/geode_lx
       device lapic 0 on end
     end
   end
diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 1245a4319c..1e82bdb70e 100644
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -118,9 +118,9 @@ static int smc_send_config(unsigned char config_data)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 static const u16 sio_init_table[] = { // hi=data, lo=index
 	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)
diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig
index 4e29742b81..2d11b33972 100644
--- a/src/mainboard/lippert/roadrunner-lx/Kconfig
+++ b/src/mainboard/lippert/roadrunner-lx/Kconfig
@@ -3,7 +3,7 @@ if BOARD_LIPPERT_ROADRUNNER_LX
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_ITE_IT8712F
diff --git a/src/mainboard/lippert/roadrunner-lx/devicetree.cb b/src/mainboard/lippert/roadrunner-lx/devicetree.cb
index eae847999a..73d1d88276 100644
--- a/src/mainboard/lippert/roadrunner-lx/devicetree.cb
+++ b/src/mainboard/lippert/roadrunner-lx/devicetree.cb
@@ -82,7 +82,7 @@ chip northbridge/amd/lx
   end
   # APIC cluster is late CPU init.
   device lapic_cluster 0 on
-    chip cpu/amd/model_lx
+    chip cpu/amd/geode_lx
       device lapic 0 on end
     end
   end
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 87718b5a1f..20e5b6a1a9 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -53,9 +53,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 static const u16 sio_init_table[] = {	// hi=data, lo=index
 	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)
diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig
index f273d6cf56..99ecf7c066 100644
--- a/src/mainboard/lippert/spacerunner-lx/Kconfig
+++ b/src/mainboard/lippert/spacerunner-lx/Kconfig
@@ -3,7 +3,7 @@ if BOARD_LIPPERT_SPACERUNNER_LX
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_ITE_IT8712F
diff --git a/src/mainboard/lippert/spacerunner-lx/devicetree.cb b/src/mainboard/lippert/spacerunner-lx/devicetree.cb
index 1fd2c54941..4bb15087db 100644
--- a/src/mainboard/lippert/spacerunner-lx/devicetree.cb
+++ b/src/mainboard/lippert/spacerunner-lx/devicetree.cb
@@ -83,7 +83,7 @@ chip northbridge/amd/lx
   end
   # APIC cluster is late CPU init.
   device lapic_cluster 0 on
-    chip cpu/amd/model_lx
+    chip cpu/amd/geode_lx
       device lapic 0 on end
     end
   end
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index 299079c852..9dcb37b4c9 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -118,9 +118,9 @@ static int smc_send_config(unsigned char config_data)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 static const u16 sio_init_table[] = { // hi=data, lo=index
 	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)
diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig
index 0a016a54f5..315b7edbf6 100644
--- a/src/mainboard/pcengines/alix1c/Kconfig
+++ b/src/mainboard/pcengines/alix1c/Kconfig
@@ -3,7 +3,7 @@ if BOARD_PCENGINES_ALIX1C
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_WINBOND_W83627HF
diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb
index 4af91ca2a4..91d935038b 100644
--- a/src/mainboard/pcengines/alix1c/devicetree.cb
+++ b/src/mainboard/pcengines/alix1c/devicetree.cb
@@ -77,7 +77,7 @@ chip northbridge/amd/lx
 
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index 7e025a88b3..f109031a8c 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -107,9 +107,9 @@ static u8 spd_read_byte(u8 device, u8 address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {
diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig
index 264f5d9e97..c2e4b2e9dd 100644
--- a/src/mainboard/pcengines/alix2d/Kconfig
+++ b/src/mainboard/pcengines/alix2d/Kconfig
@@ -3,7 +3,7 @@ if BOARD_PCENGINES_ALIX2D
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb
index edcbc06623..836ba3547c 100644
--- a/src/mainboard/pcengines/alix2d/devicetree.cb
+++ b/src/mainboard/pcengines/alix2d/devicetree.cb
@@ -37,7 +37,7 @@ chip northbridge/amd/lx
 
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 6ced8f279e..0e8cc63a16 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -106,9 +106,9 @@ static u8 spd_read_byte(u8 device, u8 address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 /** Early mainboard specific GPIO setup. */
 static void mb_gpio_init(void)
diff --git a/src/mainboard/televideo/tc7020/Kconfig b/src/mainboard/televideo/tc7020/Kconfig
index b3233d99b1..9147fc6956 100644
--- a/src/mainboard/televideo/tc7020/Kconfig
+++ b/src/mainboard/televideo/tc7020/Kconfig
@@ -21,7 +21,7 @@ if BOARD_TELEVIDEO_TC7020
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX1
+	select CPU_AMD_GEODE_GX1
 	select NORTHBRIDGE_AMD_GX1
 	select SOUTHBRIDGE_AMD_CS5530
 	select SUPERIO_NSC_PC97317
diff --git a/src/mainboard/televideo/tc7020/devicetree.cb b/src/mainboard/televideo/tc7020/devicetree.cb
index bf89cf24b1..10188a35c2 100644
--- a/src/mainboard/televideo/tc7020/devicetree.cb
+++ b/src/mainboard/televideo/tc7020/devicetree.cb
@@ -52,6 +52,6 @@ chip northbridge/amd/gx1		# Northbridge
       register "ide1_enable" = "0"	# Not available/needed on this board
     end
   end
-  chip cpu/amd/model_gx1		# CPU
+  chip cpu/amd/geode_gx1		# CPU
   end
 end
diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index dd6c8dd9fa..40679fe1f1 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -3,7 +3,7 @@ if BOARD_TRAVERSE_GEOS
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/traverse/geos/devicetree.cb b/src/mainboard/traverse/geos/devicetree.cb
index eab70c7c78..44b36f68c2 100644
--- a/src/mainboard/traverse/geos/devicetree.cb
+++ b/src/mainboard/traverse/geos/devicetree.cb
@@ -33,7 +33,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end
diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
index 80a95579d1..588681bfbb 100644
--- a/src/mainboard/traverse/geos/romstage.c
+++ b/src/mainboard/traverse/geos/romstage.c
@@ -47,9 +47,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {
diff --git a/src/mainboard/winent/pl6064/Kconfig b/src/mainboard/winent/pl6064/Kconfig
index 4f367f1fab..7db7de5791 100644
--- a/src/mainboard/winent/pl6064/Kconfig
+++ b/src/mainboard/winent/pl6064/Kconfig
@@ -3,7 +3,7 @@ if BOARD_WINENT_PL6064
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_LX
+	select CPU_AMD_GEODE_LX
 	select NORTHBRIDGE_AMD_LX
 	select SOUTHBRIDGE_AMD_CS5536
 	select SUPERIO_WINBOND_W83627HF
diff --git a/src/mainboard/winent/pl6064/devicetree.cb b/src/mainboard/winent/pl6064/devicetree.cb
index ff20fedb76..82fd21ee47 100644
--- a/src/mainboard/winent/pl6064/devicetree.cb
+++ b/src/mainboard/winent/pl6064/devicetree.cb
@@ -73,7 +73,7 @@ chip northbridge/amd/lx
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_lx
+		chip cpu/amd/geode_lx
 			device lapic 0 on end
 		end
 	end
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index a8b684e5a3..6651acd4ca 100644
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -51,9 +51,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {
diff --git a/src/mainboard/wyse/s50/Kconfig b/src/mainboard/wyse/s50/Kconfig
index dff01f99ae..982935d91d 100644
--- a/src/mainboard/wyse/s50/Kconfig
+++ b/src/mainboard/wyse/s50/Kconfig
@@ -21,7 +21,7 @@ if BOARD_WYSE_S50
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_GX2
+	select CPU_AMD_GEODE_GX2
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5536
 	select UDELAY_TSC
diff --git a/src/mainboard/wyse/s50/devicetree.cb b/src/mainboard/wyse/s50/devicetree.cb
index e7cf0c2d60..d43b81e1ab 100644
--- a/src/mainboard/wyse/s50/devicetree.cb
+++ b/src/mainboard/wyse/s50/devicetree.cb
@@ -44,7 +44,7 @@ chip northbridge/amd/gx2
 	end
 	# APIC cluster is late CPU init.
 	device lapic_cluster 0 on
-		chip cpu/amd/model_gx2
+		chip cpu/amd/geode_gx2
 			device lapic 0 on end
 		end
 	end
diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index 12fc4469ab..9e5dd5337e 100644
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -45,9 +45,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/gx2/pll_reset.c"
 #include "northbridge/amd/gx2/raminit.c"
 #include "lib/generic_sdram.c"
-#include "cpu/amd/model_gx2/cpureginit.c"
-#include "cpu/amd/model_gx2/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_gx2/cpureginit.c"
+#include "cpu/amd/geode_gx2/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
 
 void main(unsigned long bist)
 {