diff options
| author | Patrick Georgi <patrick@georgi-clan.de> | 2010-11-16 21:25:29 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-11-16 21:25:29 +0000 |
| commit | 76e8152c3924d52fc700b8eee656aa16f88f6e3a (patch) | |
| tree | e1e67d8f219ea85f7843818216d94f1a462b3e81 /src | |
| parent | 0f02daf19bd74de76a7fe5da9b4d03e767c9fc47 (diff) | |
Move the SET_FIDVID* family of configuration options to Kconfig and
make their defaults more obvious.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
61 files changed, 132 insertions, 249 deletions
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 3789fdebdf..5ec6b270c0 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -4,27 +4,50 @@ config CPU_AMD_MODEL_10XXX select SSE select SSE2 +if CPU_AMD_MODEL_10XXX config CPU_ADDR_BITS int default 48 - depends on CPU_AMD_MODEL_10XXX config DCACHE_RAM_BASE hex default 0xc4000 - depends on CPU_AMD_MODEL_10XXX config DCACHE_RAM_SIZE hex default 0x0c000 - depends on CPU_AMD_MODEL_10XXX config DCACHE_RAM_GLOBAL_VAR_SIZE hex default 0x04000 - depends on CPU_AMD_MODEL_10XXX config UDELAY_IO bool default n - depends on CPU_AMD_MODEL_10XXX + +config SET_FIDVID + bool + default y + +if SET_FIDVID +config SET_FIDVID_DEBUG + bool + default y + +config SET_FIDVID_STORE_AP_APICID_AT_FIRST + bool + default y + +config SET_FIDVID_CORE0_ONLY + bool + default n + +# 0: all cores +# 1: core 0 only +# 2: all but core 0 +config SET_FIDVID_CORE_RANGE + int + default 0 + +endif +endif diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index 22295c5654..b1a064a869 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -17,31 +17,26 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID #include <northbridge/amd/amdht/AsPsDefs.h> -#define SET_FIDVID_DEBUG 1 - -// if we are tight of CAR stack, disable it -#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 - static inline void print_debug_fv(const char *str, u32 val) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -729,7 +724,7 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid) } -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st { u32 num; // it could use 256 bytes for 64 node quad core system @@ -748,7 +743,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp) static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) { -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st ap_apicidx; u32 i; #endif @@ -806,20 +801,20 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8); print_debug_fv("BSP fid = ", fv.common_fid); -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && SET_FIDVID_CORE0_ONLY == 0 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY /* For all APs (We know the APIC ID of all APs even when the APIC ID is lifted) remote read from AP LAPIC_MSG_REG about max fid. Then calculate the common max fid that can be used for all APs and BSP */ ap_apicidx.num = 0; - for_each_ap(bsp_apicid, SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx); for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); #endif print_debug_fv("common_fid = ", fv.common_fid); diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 8f85bceb75..0498fea4d4 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -28,17 +28,6 @@ #include <cpu/x86/mtrr/earlymtrr.c> #include <northbridge/amd/amdfam10/raminit_amdmct.c> -//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID -#ifndef SET_FIDVID - #define SET_FIDVID 1 -#endif - -#ifndef SET_FIDVID_CORE0_ONLY - /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, - Need to do every AP to set common FID/VID */ - #define SET_FIDVID_CORE0_ONLY 0 -#endif - static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); void cpuSetAMDMSR(void); @@ -166,7 +155,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) return result; } -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid); #endif @@ -338,8 +327,8 @@ static u32 init_cpus(u32 cpu_init_detectedx) update_microcode(cpuid_eax(1)); cpuSetAMDMSR(); -#if SET_FIDVID == 1 -#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1) +#if CONFIG_SET_FIDVID +#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY // Run on all AP for proper FID/VID setup. if (id.coreid == 0) // only need set fid for core0 #endif @@ -928,7 +917,7 @@ static void finalize_node_setup(struct sys_info *sysinfo) cpuSetAMDPCI(i); } -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID // Prep each node for FID/VID setup. prep_fid_change(); #endif diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 139b96ad25..962b399e03 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -4,7 +4,31 @@ config CPU_AMD_MODEL_FXX select SSE select SSE2 +if CPU_AMD_MODEL_FXX config UDELAY_IO bool default n - depends on CPU_AMD_MODEL_FXX + +config SET_FIDVID + bool + default n + default y if K8_REV_F_SUPPORT + +if SET_FIDVID +config SET_FIDVID_DEBUG + bool + default n + +config SET_FIDVID_CORE0_ONLY + bool + default y + +config SET_FIDVID_ONE_BY_ONE + bool + default y + +config SET_FIDVID_STORE_AP_APICID_AT_FIRST + bool + default y +endif +endif diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index bfbc93d577..bbafde6662 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -1,10 +1,4 @@ -#if SET_FIDVID == 1 - -#define SET_FIDVID_DEBUG 0 - -#define SET_FIDVID_ONE_BY_ONE 1 - -#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 +#if CONFIG_SET_FIDVID #ifndef SB_VFSMAF #define SB_VFSMAF 1 @@ -14,21 +8,21 @@ static inline void print_debug_fv(const char *str, u32 val) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -70,7 +64,7 @@ static void enable_fid_change(void) } } -#if SET_FIDVID_ONE_BY_ONE == 0 +#if !CONFIG_SET_FIDVID_ONE_BY_ONE static unsigned set_fidvid_without_init(unsigned fidvid) { msr_t msr; @@ -276,7 +270,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) ldtstop_sb(); #endif -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG if (showmessage) { print_debug_fv_8("set_fidvid APICID = ", apicid); print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo); @@ -290,7 +284,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) } fid_cur = msr.lo & 0x3f; -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG if (showmessage) { print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo); } @@ -368,7 +362,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16; /* max vid */ send |= (apicid << 24); /* ap apicid */ -#if SET_FIDVID_ONE_BY_ONE == 1 +#if CONFIG_SET_FIDVID_ONE_BY_ONE vid_cur = msr.hi & 0x3f; fid_cur = msr.lo & 0x3f; @@ -399,7 +393,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) } if (loop > 0) { -#if SET_FIDVID_ONE_BY_ONE == 1 +#if CONFIG_SET_FIDVID_ONE_BY_ONE readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP #else readback = set_fidvid_without_init(readback & 0xffff00); // this AP @@ -502,7 +496,7 @@ static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp) print_debug_fv("\treadback=", readback); } -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st { u32 num; unsigned apicid[16]; /* 8 way dual core need 16 */ @@ -524,7 +518,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) struct fidvid_st fv; -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st ap_apicidx; unsigned i; #endif @@ -551,16 +545,16 @@ static void init_fidvid_bsp(unsigned bsp_apicid) /* calculate the common max fid/vid that could be used for * all APs and BSP */ -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST ap_apicidx.num = 0; - for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx); for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); #endif #if 0 @@ -587,7 +581,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) #endif -#if SET_FIDVID_ONE_BY_ONE == 1 +#if CONFIG_SET_FIDVID_ONE_BY_ONE /* set BSP fid and vid */ print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); @@ -601,15 +595,15 @@ static void init_fidvid_bsp(unsigned bsp_apicid) fv.common_fidvid &= 0xffff00; /* set state 2 allow is in init_fidvid_bsp_stage2 */ -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv); #endif -#if SET_FIDVID_ONE_BY_ONE == 0 +#if !CONFIG_SET_FIDVID_ONE_BY_ONE /* set BSP fid and vid */ print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 5672a6e8f1..570cb4e585 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -2,22 +2,6 @@ #include "option_table.h" #endif -//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID -#ifndef SET_FIDVID -#if CONFIG_K8_REV_F_SUPPORT == 0 - #define SET_FIDVID 0 -#else - // for rev F, need to set FID to max - #define SET_FIDVID 1 -#endif - -#endif - -#ifndef SET_FIDVID_CORE0_ONLY - /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice */ - #define SET_FIDVID_CORE0_ONLY 1 -#endif - typedef void (*process_ap_t) (u32 apicid, void *gp); //core_range = 0 : all cores @@ -135,7 +119,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) #define LAPIC_MSG_REG 0x380 -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID static void init_fidvid_ap(u32 bsp_apicid, u32 apicid); #endif @@ -291,8 +275,8 @@ static u32 init_cpus(u32 cpu_init_detectedx) u32 timeout = 1; u32 loop = 100; -#if SET_FIDVID == 1 -#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1) +#if CONFIG_SET_FIDVID +#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY if (id.coreid == 0) // only need set fid for core0 #endif init_fidvid_ap(bsp_apicid, apicid); diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index 8a3e900364..d585aac692 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 3da0fd52eb..89b744b98e 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig index 6e2239b5e3..4e926d83ce 100644 --- a/src/mainboard/amd/mahogany/Kconfig +++ b/src/mainboard/amd/mahogany/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select GFXUMA select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 7fb715bc5f..869d28b64e 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 0c360ff256..49d042fe75 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -27,10 +27,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -196,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index 94134584c7..b77efb3fdd 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 5e14322478..4da287abf1 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 69d7dcdaab..b08081b407 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -1,10 +1,5 @@ #define SET_NB_CFG_54 1 -//used by init_cpus and fidvid -#define SET_FIDVID 0 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -150,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset; unsigned bsp_apicid = 0; -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID struct cpuid_result cpuid1; #endif @@ -214,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index a908913cf4..d9491c7498 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -27,10 +27,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -195,7 +191,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 273d7a8b43..3c4606d3cf 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -27,10 +27,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -196,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig index e08bf91d97..79901692de 100644 --- a/src/mainboard/asrock/939a785gmh/Kconfig +++ b/src/mainboard/asrock/939a785gmh/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 4e1ee79c03..d42a6268ef 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig index 70caf20cf4..6f85872dcf 100644 --- a/src/mainboard/asus/a8v-e_deluxe/Kconfig +++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 008a345d83..aab0377592 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -24,12 +24,6 @@ unsigned int get_sbdn(unsigned bus); -/* Used by init_cpus and fidvid */ -#define SET_FIDVID 1 - -/* If we want to wait for core1 done before DQS training, set it to 0. */ -#define SET_FIDVID_CORE0_ONLY 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig index c5d3394cfa..2c0ac0476f 100644 --- a/src/mainboard/asus/a8v-e_se/Kconfig +++ b/src/mainboard/asus/a8v-e_se/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 008a345d83..aab0377592 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -24,12 +24,6 @@ unsigned int get_sbdn(unsigned bus); -/* Used by init_cpus and fidvid */ -#define SET_FIDVID 1 - -/* If we want to wait for core1 done before DQS training, set it to 0. */ -#define SET_FIDVID_CORE0_ONLY 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index ea25cb3713..9e3b2649a6 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -37,6 +37,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select TINY_BOOTBLOCK select HAVE_MAINBOARD_RESOURCES select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index f252b3d220..91a75adfb8 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -24,12 +24,6 @@ unsigned int get_sbdn(unsigned bus); -/* Used by init_cpus and fidvid */ -#define SET_FIDVID 1 - -/* If we want to wait for core1 done before DQS training, set it to 0. */ -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig index 3b405abc41..f842455192 100644 --- a/src/mainboard/asus/m2v/Kconfig +++ b/src/mainboard/asus/m2v/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 012ca09a0f..80aa43d99f 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -27,10 +27,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -197,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index 395c75e5bc..85a89d09e3 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 69d068dd3b..d688713e0f 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -25,11 +25,6 @@ #define SET_NB_CFG_54 1 #endif -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -212,7 +207,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index db8465ee93..4abe1c8744 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 1045a573ab..dd84ebfa18 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -23,11 +23,6 @@ #define SET_NB_CFG_54 1 #endif -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -223,7 +218,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index bca7eb5120..8b43f6d613 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -23,10 +23,6 @@ #define SET_NB_CFG_54 1 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -192,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index ed8a15e6b1..d21644c721 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -27,10 +27,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -195,7 +191,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index b5b75a53f4..e4c1aa8d3b 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 883ee32a2f..330d4a51df 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -29,11 +29,6 @@ #define SET_NB_CFG_54 1 #endif -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -229,7 +224,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn bcm5785_early_setup(); -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index c2f5ac0d67..89b495ece9 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -33,9 +33,6 @@ #define SET_NB_CFG_54 1 #endif -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -187,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_other_cores_started(bsp_apicid); #endif -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index f0ea2acfef..03139d9494 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -29,10 +29,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - /* UART address and device number */ #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) @@ -201,7 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index fb5a6b5474..c3f75e8ce0 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -1,10 +1,5 @@ #define SET_NB_CFG_54 1 -//used by init_cpus and fidvid -#define SET_FIDVID 0 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -171,7 +166,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 39f60e006e..d22591095f 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -1,10 +1,5 @@ #define SET_NB_CFG_54 1 -//used by init_cpus and fidvid -#define SET_FIDVID 0 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -171,7 +166,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 39f60e006e..d22591095f 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -1,10 +1,5 @@ #define SET_NB_CFG_54 1 -//used by init_cpus and fidvid -#define SET_FIDVID 0 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -171,7 +166,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index c89893b5cf..f8c7e11f37 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -28,10 +28,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -204,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index 376518ddb3..950cb78b1f 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 3f084b36dc..03f81f2485 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index bd9bbe072b..4cfcc1749b 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 9804518c0d..210ea4f8fe 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -28,12 +28,6 @@ #define SET_NB_CFG_54 1 #endif -/* Used by init_cpus and fidvid. */ -#define SET_FIDVID 1 - -/* If we want to wait for core1 done before DQS training, set it to 0. */ -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -201,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Set up chains and store link pair for optimization later. */ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr = rdmsr(0xc0010042); print_debug("begin msr fid, vid "); diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig index ebae5d137e..2d3041ca22 100644 --- a/src/mainboard/msi/ms9185/Kconfig +++ b/src/mainboard/msi/ms9185/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index bc6ead6a75..599a01a37e 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -25,11 +25,6 @@ #define SET_NB_CFG_54 1 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -201,7 +196,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 942fb11989..6f24bdccfc 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -24,12 +24,6 @@ #define SET_NB_CFG_54 1 -// used by init_cpus and fidvid (disabled until someone tests this) -// #define SET_FIDVID 1 -#define SET_FIDVID 0 -// if we want to wait for core1 done before DQS training, set it to 0 -// #define SET_FIDVID_CORE0_ONLY 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 5ad0719fa7..18618589c7 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -27,9 +27,6 @@ #define SET_NB_CFG_54 1 #endif -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -224,7 +221,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 5cc933d4c0..07ab0b0945 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -23,11 +23,6 @@ #define SET_NB_CFG_54 1 #endif -//used by init_cpus and fidvid -#define SET_FIDVID 0 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -210,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index 10fcbb368e..08151a0ec4 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index cb6d8ecddb..c1c597bcfc 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -20,11 +20,6 @@ #define SET_NB_CFG_54 1 #endif -// used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -269,7 +264,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index 5056446328..77103300b4 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 4abb4d099e..1cf2446c29 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -23,11 +23,6 @@ #define SET_NB_CFG_54 1 #endif -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -198,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 294677c5c1..06347db2ab 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -27,9 +27,6 @@ #define SET_NB_CFG_54 1 #endif -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -214,7 +211,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index ee858a89cd..5e7b32b4d9 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -27,9 +27,6 @@ #define SET_NB_CFG_54 1 #endif -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -256,7 +253,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 2efd978d53..095f36d67f 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 2f61667dbb..f840e087c7 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 953966b8dc..a38d875050 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 5426eb4a34..26738a323e 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 2f0ef20916..20b6baadbd 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -23,11 +23,6 @@ #define SET_NB_CFG_54 1 #endif -//used by init_cpus and fidvid -#define SET_FIDVID 0 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -205,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 61c253bf47..8439740ffb 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -27,9 +27,6 @@ #define SET_NB_CFG_54 1 #endif -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -216,7 +213,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |