diff options
| author | Alexandru Gagniuc <alexandrux.gagniuc@intel.com> | 2016-05-03 11:25:03 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-06 18:57:56 +0200 |
| commit | 665fca156c2c22884b5b796e3f365f5d5ed61733 (patch) | |
| tree | 27d38acf2aa0594118fa7e26b02b7aa351f23d00 /src | |
| parent | 532f319c9d5504b6b1f6a044e138c4c62e6311b4 (diff) | |
intel/amenia: Declare ChromeEC in devicetree.cb
This allows the chomeec driver to declare its resources so that IO
windows to LPC are opened up during resource allocation.
Change-Id: Ife98ecb4cbf5393493e6c71742de8d37953df548
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14591
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/amenia/devicetree.cb | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index c54e838826..38a2de2c43 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -46,7 +46,11 @@ chip soc/intel/apollolake device pci 1b.0 on end # - SDCARD device pci 1c.0 on end # - eMMC device pci 1e.0 on end # - SDIO - device pci 1f.0 on end # - LPC + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end device pci 1f.1 on end # - SMBUS end end |