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authorAaron Durbin <adurbin@chromium.org>2013-05-10 00:51:43 -0500
committerAaron Durbin <adurbin@google.com>2013-05-16 01:30:25 +0200
commit5b54d353aa89685c1cde0d6254a9899cf327a712 (patch)
treeaf56367788f69a4ab61040ae16b15806b2b1b0dd /src
parent2ad6bd23a7ebcaf593f717db9c356284237ed639 (diff)
haswell: enable cache-as-ram migration
The haswell code allows for vboot ramstage verification. However, that code path relies on accessing global cache-as-ram variables after cache-as-ram is torn down. In order to avoid that situation enable cache-as-ram migration. cbmemc_reinit() no longer needs to be called from romstage because it is invoked automatically by the cache-as-ram migration infrastructure. Change-Id: I08998dca579c167699030e1e24ea0af8802c0758 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3236 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/haswell/Kconfig1
-rw-r--r--src/cpu/intel/haswell/romstage.c5
2 files changed, 1 insertions, 5 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 152059fcbe..4c61b2d1da 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+ select CAR_MIGRATION
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 1093e6b1e5..8196273195 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -188,11 +188,6 @@ void * asmlinkage romstage_main(unsigned long bist)
/* Get the stack to use after cache-as-ram is torn down. */
romstage_stack_after_car = setup_romstage_stack_after_car();
-#if CONFIG_CONSOLE_CBMEM
- /* Keep this the last thing this function does. */
- cbmemc_reinit();
-#endif
-
return romstage_stack_after_car;
}