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authorJack Rosenthal <jrosenth@chromium.org>2020-12-16 13:35:46 -0700
committerHung-Te Lin <hungte@chromium.org>2020-12-28 13:37:56 +0000
commit32ed65611d796d507dd004d9a2d97d38b3c2ce7e (patch)
treef6d3a3292964902cb6f138d9df3b29f8f784f219 /src
parentd0701c96f20d4b3d04c42c13b1e015d6aa27f1d4 (diff)
kconfig: remove non-existent source
src/northbridge/amd/pi/00660F01/Kconfig does not exist. Remove the source statement. Also, no kconfig files under src/soc/intel/common/basecode/. Clean that up. Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I10917b76ff6c2a9d5a97d5c7dfa9e8925cd8c8a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/amd/pi/Kconfig1
-rw-r--r--src/soc/intel/common/basecode/Kconfig7
2 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
index 833afae9df..15e685b211 100644
--- a/src/northbridge/amd/pi/Kconfig
+++ b/src/northbridge/amd/pi/Kconfig
@@ -29,7 +29,6 @@ config S3_VGA_ROM_RUN
source "src/northbridge/amd/pi/00630F01/Kconfig"
source "src/northbridge/amd/pi/00730F01/Kconfig"
-source "src/northbridge/amd/pi/00660F01/Kconfig"
config HW_MEM_HOLE_SIZEK
hex
diff --git a/src/soc/intel/common/basecode/Kconfig b/src/soc/intel/common/basecode/Kconfig
index 1c93244573..9e0f788eb4 100644
--- a/src/soc/intel/common/basecode/Kconfig
+++ b/src/soc/intel/common/basecode/Kconfig
@@ -2,10 +2,3 @@ config SOC_INTEL_COMMON_BASECODE
bool
help
Common coreboot stages and non-IP block for Intel platform
-
-if SOC_INTEL_COMMON_BASECODE
-
-source "src/soc/intel/common/basecode/*/Kconfig"
-source "src/soc/intel/common/basecode/*/*/Kconfig"
-
-endif