diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-02-10 17:10:05 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-02-15 08:05:41 +0100 |
| commit | 3054c8b7542f5393ee2ac1272525764ffecb52d0 (patch) | |
| tree | 0ea202dce3a8a25f78d543e34fa701bcdf8c096a /src | |
| parent | 73b753a7f50d7435d1ba3ef763a910a30ee32d16 (diff) | |
skylake: Enable DDI-A 4-lane support if GOP does not execute
This change will allow the kernel to use 4-lane eDP connections
if the GOP driver does not execute and set this bit. If GOP
has executed (everyone but Chrome OS verified mode) the link will
already be up and this will do nothing.
BUG=chrome-os-partner:50197
BRANCH=glados
TEST=boot on chell and ensure 4
Change-Id: I9e2328b00db84f26b9bd03220b8ac0bd5f64cfbf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cff83e18ce9936c8d507f93c8443b7056c62e844
Original-Change-Id: I3f1e5d78b91eb0e4a23fcc196aff0edadc252a0c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/327251
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13690
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/igd.c | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c index b87467f4a5..4bb597c64c 100644 --- a/src/soc/intel/skylake/igd.c +++ b/src/soc/intel/skylake/igd.c @@ -62,6 +62,23 @@ static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask) static void igd_init(struct device *dev) { + u32 ddi_buf_ctl; + + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!gtt_res || !gtt_res->base) + return; + + /* + * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. + * This will allow the kernel to use 4-lane eDP links properly + * if the VBIOS or GOP driver does not execute. + */ + ddi_buf_ctl = gtt_read(DDI_BUF_CTL_A); + if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { + ddi_buf_ctl |= DDI_A_4_LANES; + gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); + } + if (IS_ENABLED(CONFIG_GOP_SUPPORT)) return; @@ -70,10 +87,6 @@ static void igd_init(struct device *dev) reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!gtt_res || !gtt_res->base) - return; - /* Wait for any configured pre-graphics delay */ if (!acpi_is_wakeup_s3()) { #if IS_ENABLED(CONFIG_CHROMEOS) |