driver/intel/fsp20: move lb_framebuffer function

move lb_framebuffer function in soc/intel/apollolake
to driver/intel/fsp20 so that fsp 2.0 bases soc's can
use common lb_framebuffer function.

Change-Id: If11bc7faa378a39cf7d4487f9095465a4df84853
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16549
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

4 files changed, 44 insertions, 23 deletions

diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c
index 039202faa4..caf7bfa807 100644
--- a/src/drivers/intel/fsp2_0/graphics.c
+++ b/src/drivers/intel/fsp2_0/graphics.c
@@ -103,3 +103,38 @@ uintptr_t fsp_load_vbt(void)
 
 	return (uintptr_t)vbt;
 }
+
+void lb_framebuffer(struct lb_header *header)
+{
+	enum cb_err ret;
+	struct lb_framebuffer *framebuffer;
+	uintptr_t framebuffer_bar;
+
+	/* Pci enumeration happens after silicon init.
+	 * After enumeration graphic framebuffer base may be relocated.
+	 * Get framebuffer base from soc.
+	 */
+	framebuffer_bar = fsp_soc_get_igd_bar();
+
+	if (!framebuffer_bar) {
+		printk(BIOS_ALERT, "Framebuffer BAR invalid\n");
+		return;
+	}
+
+	framebuffer = (void *)lb_new_record(header);
+	ret = fsp_fill_lb_framebuffer(framebuffer);
+	if (ret != CB_SUCCESS) {
+		printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n");
+		return;
+	}
+
+	/* Resource allocator can move the BAR around after FSP configures it */
+	framebuffer->physical_address = framebuffer_bar;
+	printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n",
+		framebuffer->physical_address);
+}
+
+__attribute__((weak)) uintptr_t fsp_soc_get_igd_bar(void)
+{
+	return 0;
+}
\ No newline at end of file
diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
index 1c8dbba024..acb41e0c4d 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/util.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/util.h
@@ -77,6 +77,9 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr,
 /* Load a vbt.bin file for graphics. Returns 0 if a valid VBT is not found. */
 uintptr_t fsp_load_vbt(void);
 
+/* Get igd framebuffer bar from SoC */
+uintptr_t fsp_soc_get_igd_bar(void);
+
 /*
  * Handle FSP reboot request status. Chipset/soc is expected to provide
  * chipset_handle_reset() that deals with reset type codes specific to given
diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c
index ba3d5dbf2b..9b4dbc97da 100644
--- a/src/soc/intel/apollolake/graphics.c
+++ b/src/soc/intel/apollolake/graphics.c
@@ -22,37 +22,17 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <soc/pci_devs.h>
 #include <soc/pci_ids.h>
 #include <soc/intel/common/opregion.h>
 
-static uintptr_t framebuffer_bar = (uintptr_t)NULL;
-
-void lb_framebuffer(struct lb_header *header)
+uintptr_t fsp_soc_get_igd_bar(void)
 {
-	enum cb_err ret;
-	struct lb_framebuffer *framebuffer;
-
-	framebuffer = (void *)lb_new_record(header);
-	ret = fsp_fill_lb_framebuffer(framebuffer);
-	if (ret != CB_SUCCESS) {
-		printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n");
-		return;
-        }
-
-	if (!framebuffer_bar) {
-		printk(BIOS_ALERT, "Framebuffer BAR invalid (00:02.0 BAR2)\n");
-		return;
-	}
-
-	/* Resource allocator can move the BAR around after FSP configures it */
-	framebuffer->physical_address = framebuffer_bar;
-	printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n",
-	       framebuffer->physical_address);
+	return find_resource(IGD_DEV, PCI_BASE_ADDRESS_2)->base;
 }
 
 static void igd_set_resources(struct device *dev)
 {
-	framebuffer_bar = find_resource(dev, PCI_BASE_ADDRESS_2)->base;
 	pci_dev_set_resources(dev);
 }
 
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
index b7519ed799..0d9e28847c 100644
--- a/src/soc/intel/apollolake/include/soc/pci_devs.h
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -34,6 +34,9 @@
 #define NB_DEVFN			_PCI_DEVFN(0, 0)
 #define NB_DEV_ROOT			_PCI_DEV(0x0, 0)
 
+#define IGD_DEV				_PCI_DEV(0x2, 0)
+#define IGD_DEVFN			_PCI_DEVFN(0x2, 0)
+
 #define P2SB_DEV			_PCI_DEV(0xd, 0)
 #define P2SB_DEVFN			_PCI_DEVFN(0xd, 0)