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authorZhuo-hao Lee <zhuo-hao.lee@intel.com>2017-03-14 10:27:28 +0800
committerAaron Durbin <adurbin@chromium.org>2017-03-17 03:36:09 +0100
commit07f60aa56fefa0aeb4f896d63267a54ddfae0715 (patch)
tree4ea54d893074df433f7c5f24e75fdd4abf30c930 /src
parent6f80ccc357702f87baf43440d97a49bcce999393 (diff)
soc/intel/apollolake: Reduce D3 cold delay for eMMC controller
eMMC Controller is taking over 100ms to resume during runtime which results in I/O latency issues on the Apollo Lake system such as Snappy. The cause is the Linux Kernel setting the firmware reset time to 100 ms by default. This patch adds _DSM method for eMMC comtroller for specifying the device readiness durations. Function index 9 returns package of five integers to set D3 cold delay to zero and ACPI constant Ones for the elements where overriding the default values is not desired. BUG=b:35774937 BRANCH=none TEST=update snappy coreboot and test i/o latency is under 100ms Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee@intel.com> Signed-off-by: Sowmya V <v.sowmya@intel.com> Change-Id: Idcfe4252b20bead15c2e5b9cb000ff797295f06a Reviewed-on: https://review.coreboot.org/18806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/acpi/scs.asl43
1 files changed, 43 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl
index 05aedca5a4..f69f43cda5 100644
--- a/src/soc/intel/apollolake/acpi/scs.asl
+++ b/src/soc/intel/apollolake/acpi/scs.asl
@@ -47,6 +47,49 @@ Scope (\_SB.PCI0) {
Device (SDHA) {
Name (_ADR, 0x001C0000)
Name (_DDN, "Intel(R) eMMC Controller - 80865ACC")
+ Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))
+
+ /*
+ * Device Specific Method
+ * Arg0 - UUID
+ * Arg1 - Revision
+ * Arg2 - Function Index
+ */
+ Method (_DSM, 4)
+ {
+ If (LEqual (Arg0, ^UUID)) {
+ /*
+ * Function 9: Device Readiness Durations
+ * Returns a package of five integers covering
+ * various device related delays in PCIe Base Spec.
+ */
+ If (LEqual (Arg2, 9)) {
+ /*
+ * Function 9 support for revision 3.
+ * ECN link for function definitions
+ * [https://pcisig.com/sites/default/files/
+ * specification_documents/
+ * ECN_fw_latency_optimization_final.pdf]
+ */
+ If (LEqual (Arg1, 3)) {
+ /*
+ * Integer 0: FW reset time.
+ * Integer 1: FW data link up time.
+ * Integer 2: FW functional level reset
+ * time.
+ * Integer 3: FW D3 hot to D0 time.
+ * Integer 4: FW VF enable time.
+ * set ACPI constant Ones for elements
+ * where overriding the default value
+ * is not desired.
+ */
+ Return (Package (5) {0, Ones, Ones,
+ Ones, Ones})
+ }
+ }
+ }
+ Return (Buffer() { 0x00 })
+ }
Method (_PS0, 0, NotSerialized)
{