no warnings day

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

16 files changed, 91 insertions, 70 deletions

diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h
index 661e5f348e..580f27831b 100644
--- a/src/northbridge/amd/amdk8/amdk8_f.h
+++ b/src/northbridge/amd/amdk8/amdk8_f.h
@@ -522,7 +522,7 @@ struct sys_info {
 
 #if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \
 	((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__))
-static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
+static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 {
 
 	int i;
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 39182854eb..9a60ecc03e 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -153,6 +153,7 @@ static void disable_probes(void)
 
 }
 
+#if 0
 static void enable_apic_ext_id(u8 node)
 {
 #if CONFIG_ENABLE_APIC_EXT_ID==1
@@ -165,6 +166,7 @@ static void enable_apic_ext_id(u8 node)
 	pci_write_config32(NODE_HT(node), 0x68, val);
 #endif
 }
+#endif
 
 static void enable_routing(u8 node)
 {
@@ -378,6 +380,7 @@ static uint8_t get_linkn_first(uint8_t byte)
 	return byte;
 }
 
+#if TRY_HIGH_FIRST == 1
 static uint8_t get_linkn_last(uint8_t byte)
 {
 	if(byte & 0x02) { byte &= 0x0f; byte |= 0x00;  }
@@ -385,7 +388,9 @@ static uint8_t get_linkn_last(uint8_t byte)
 	if(byte & 0x08) { byte &= 0x0f; byte |= 0x20;  }
 	return byte>>4;
 }
+#endif
 
+#if (CONFIG_MAX_PHYSICAL_CPUS > 2) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
 static uint8_t get_linkn_last_count(uint8_t byte)
 {
 	byte &= 0x0f;
@@ -394,6 +399,7 @@ static uint8_t get_linkn_last_count(uint8_t byte)
 	if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
 	return byte>>4;
 }
+#endif
 
 static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/
 {
@@ -484,10 +490,12 @@ static void setup_temp_row(u8 source, u8 dest)
 	fill_row(source,7,get_row(source,dest));
 }
 
+#if 0
 static void clear_temp_row(u8 source)
 {
 	fill_row(source, 7, DEFAULT);
 }
+#endif
 
 static void setup_remote_node(u8 node)
 {
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index b4e3d64d63..4e295d3323 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -67,10 +67,12 @@ static uint8_t ht_lookup_slave_capability(device_t dev)
 	return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format
 }
 
+#if 0
 static uint8_t ht_lookup_host_capability(device_t dev)
 {
 	return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
 }
+#endif
 
 static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid)
 {
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 5cd6d53688..5a82c51dc3 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -1824,12 +1824,12 @@ static void set_sysinfo_in_ram(unsigned val)
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 #else
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
+static int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {
 	return nvram_pos;
 }
 
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 {
 	die("No memory NVRAM loader for DQS data! Unable to restore memory state\n");
 
@@ -1837,12 +1837,14 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 }
 #endif
 
+#if CONFIG_MEM_TRAIN_SEQ == 0
 static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
 {
 	u32 dword = pci_read_config32_index_wait(dev, 0x98, index);
 
 	return s3_save_nvram_early(dword, size, nvram_pos);
 }
+#endif
 
 static int load_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
 {
diff --git a/src/southbridge/amd/amd8111/amd8111_reset.c b/src/southbridge/amd/amd8111/amd8111_reset.c
index e3c061d457..9b26bcb90d 100644
--- a/src/southbridge/amd/amd8111/amd8111_reset.c
+++ b/src/southbridge/amd/amd8111/amd8111_reset.c
@@ -1,4 +1,5 @@
 #include <arch/io.h>
+#include <reset.h>
 #include <device/pci_ids.h>
 
 #define PCI_DEV(BUS, DEV, FN) ( \
diff --git a/src/southbridge/amd/rs780/rs780_early_setup.c b/src/southbridge/amd/rs780/rs780_early_setup.c
index 2ebda9a7da..236d95fef9 100644
--- a/src/southbridge/amd/rs780/rs780_early_setup.c
+++ b/src/southbridge/amd/rs780/rs780_early_setup.c
@@ -177,6 +177,7 @@ static u8 is_famly10(void)
 	return (cpuid_eax(1) & 0xff00000) != 0;
 }
 
+#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1		/* save some spaces */
 static u8 l3_cache(void)
 {
 	return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
@@ -186,6 +187,7 @@ static u8 cpu_core_number(void)
 {
 	return (cpuid_ecx(0x80000008) & 0xFF) + 1;
 }
+#endif
 
 static u8 get_nb_rev(device_t nb_dev)
 {
diff --git a/src/southbridge/sis/sis966/sis966_aza.c b/src/southbridge/sis/sis966/sis966_aza.c
index 60c99706fe..c7573a3f7a 100644
--- a/src/southbridge/sis/sis966/sis966_aza.c
+++ b/src/southbridge/sis/sis966/sis966_aza.c
@@ -32,7 +32,7 @@
 #include <delay.h>
 #include "sis966.h"
 
-uint8_t	SiS_SiS7502_init[7][3]={
+u8	SiS_SiS7502_init[7][3]={
 {0x04, 0xFF, 0x07},
 {0x2C, 0xFF, 0x39},
 {0x2D, 0xFF, 0x10},
@@ -42,9 +42,9 @@ uint8_t	SiS_SiS7502_init[7][3]={
 {0x00, 0x00, 0x00}					//End of table
 };
 
-static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
+static int set_bits(u32 port, u32 mask, u32 val)
 {
-	uint32_t dword;
+	u32 dword;
 	int count;
 
 	val &= mask;
@@ -67,11 +67,9 @@ static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
 
 }
 
- uint32_t send_verb(uint8_t *base, uint32_t verb)
+static u32 send_verb(u32 base, u32 verb)
 {
-
-
-     uint32_t dword;
+     u32 dword;
 
      dword = read32(base + 0x68);
      dword=dword|(unsigned long)0x0002;
@@ -91,13 +89,12 @@ static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
 
      dword = read32(base + 0x64);
      return dword;
-
 }
 
 
-static int codec_detect(uint8_t *base)
+static int codec_detect(u32 base)
 {
-	uint32_t dword;
+	u32 dword;
 	int idx=0;
 
 	/* 1 */ // controller reset
@@ -125,7 +122,7 @@ static int codec_detect(uint8_t *base)
 }
 
 
-static uint32_t verb_data[] = {
+static u32 verb_data[] = {
 
 //14
 	0x01471c10,
@@ -189,18 +186,18 @@ static uint32_t verb_data[] = {
 	0x01f71f01,
 };
 
-static unsigned find_verb(uint32_t viddid, uint32_t **verb)
+static unsigned find_verb(u32 viddid, u32 **verb)
 {
         if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0;
-	*verb =  (uint32_t *)verb_data;
-	return sizeof(verb_data)/sizeof(uint32_t);
+	*verb =  (u32 *)verb_data;
+	return sizeof(verb_data)/sizeof(u32);
 }
 
 
-static void codec_init(uint8_t *base, int addr)
+static void codec_init(u32 base, int addr)
 {
-	uint32_t dword;
-	uint32_t *verb;
+	u32 dword;
+	u32 *verb;
 	unsigned verb_size;
 	int i;
 
@@ -235,7 +232,7 @@ static void codec_init(uint8_t *base, int addr)
 	printk(BIOS_DEBUG, "verb loaded!\n");
 }
 
-static void codecs_init(uint8_t *base, uint32_t codec_mask)
+static void codecs_init(u32 base, u32 codec_mask)
 {
 	codec_init(base, 0);
 	return;
@@ -243,15 +240,15 @@ static void codecs_init(uint8_t *base, uint32_t codec_mask)
 
 static void aza_init(struct device *dev)
 {
-        uint8_t *base;
+        u32 base;
         struct resource *res;
-        uint32_t codec_mask;
+        u32 codec_mask;
 
         print_debug("AZALIA_INIT:---------->\n");
 
 //-------------- enable AZA (SiS7502) -------------------------
 {
-        uint8_t  temp8;
+        u8  temp8;
         int i=0;
         while(SiS_SiS7502_init[i][0] != 0)
         {
@@ -292,8 +289,8 @@ static void aza_init(struct device *dev)
 	if(!res)
 		return;
 
-	base =(uint8_t *) res->base;
-	printk(BIOS_DEBUG, "base = %p\n", base);
+	base = res->base;
+	printk(BIOS_DEBUG, "base = 0x%08x\n", base);
 
 	codec_mask = codec_detect(base);
 
diff --git a/src/southbridge/sis/sis966/sis966_early_ctrl.c b/src/southbridge/sis/sis966/sis966_early_ctrl.c
index 73e34b47c9..05b53365de 100644
--- a/src/southbridge/sis/sis966/sis966_early_ctrl.c
+++ b/src/southbridge/sis/sis966/sis966_early_ctrl.c
@@ -19,6 +19,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <reset.h>
+
 static unsigned get_sbdn(unsigned bus)
 {
 	device_t dev;
@@ -31,7 +33,7 @@ static unsigned get_sbdn(unsigned bus)
 	return (dev>>15) & 0x1f;
 }
 
-static void hard_reset(void)
+void hard_reset(void)
 {
 	set_bios_reset();
 
@@ -42,12 +44,11 @@ static void hard_reset(void)
 
 static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
 {
-/* default value for sis966 is good */
+	/* default value for sis966 is good */
 	/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
-
 }
 
-static void soft_reset(void)
+void soft_reset(void)
 {
 	set_bios_reset();
 
diff --git a/src/southbridge/sis/sis966/sis966_early_smbus.c b/src/southbridge/sis/sis966/sis966_early_smbus.c
index 0f40872a4d..3d4954b64f 100644
--- a/src/southbridge/sis/sis966/sis966_early_smbus.c
+++ b/src/southbridge/sis/sis966/sis966_early_smbus.c
@@ -344,7 +344,7 @@ static const uint8_t	SiS_SiS1183_init[44][3]={
                             => 04h :  128MBytes
                             => Others:  Reserved
 */
-void Init_Share_Memory(uint8_t ShareSize)
+static void Init_Share_Memory(uint8_t ShareSize)
 {
     device_t dev;
 
@@ -360,7 +360,7 @@ void Init_Share_Memory(uint8_t ShareSize)
                => 04h :  512MBytes
                => Others:  Reserved
 */
-void Init_Aper_Size(uint8_t AperSize)
+static void Init_Aper_Size(uint8_t AperSize)
 {
         device_t dev;
         uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
@@ -372,7 +372,7 @@ void Init_Aper_Size(uint8_t AperSize)
         pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
 }
 
-void sis_init_stage1(void)
+static void sis_init_stage1(void)
 {
         device_t dev;
         uint8_t temp8;
@@ -434,7 +434,7 @@ void sis_init_stage1(void)
 
 
 
-void sis_init_stage2(void)
+static void sis_init_stage2(void)
 {
 	device_t dev;
 	msr_t	msr;
diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c
index 39f1996ff4..fc73e39431 100644
--- a/src/southbridge/sis/sis966/sis966_lpc.c
+++ b/src/southbridge/sis/sis966/sis966_lpc.c
@@ -55,6 +55,8 @@
 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL	MAINBOARD_POWER_ON
 #endif
 
+#undef SLAVE_INIT
+
 static void lpc_common_init(device_t dev)
 {
 	uint8_t byte;
@@ -69,11 +71,12 @@ static void lpc_common_init(device_t dev)
 	setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
 }
 
+#ifdef SLAVE_INIT
 static void lpc_slave_init(device_t dev)
 {
 	lpc_common_init(dev);
 }
-
+#endif
 
 static void lpc_usb_legacy_init(device_t dev)
 {
@@ -271,12 +274,14 @@ static struct device_operations lpc_ops  = {
 //	.enable		= sis966_enable,
 	.ops_pci	= &lops_pci,
 };
+
 static const struct pci_driver lpc_driver __pci_driver = {
 	.ops	= &lpc_ops,
 	.vendor	= PCI_VENDOR_ID_SIS,
 	.device	= PCI_DEVICE_ID_SIS_SIS966_LPC,
 };
 
+#ifdef SLAVE_INIT // No device? 
 static struct device_operations lpc_slave_ops  = {
 	.read_resources	= sis966_lpc_read_resources,
 	.set_resources	= pci_dev_set_resources,
@@ -285,3 +290,4 @@ static struct device_operations lpc_slave_ops  = {
 //	.enable		= sis966_enable,
 	.ops_pci	= &lops_pci,
 };
+#endif
diff --git a/src/southbridge/sis/sis966/sis966_nic.c b/src/southbridge/sis/sis966/sis966_nic.c
index b9cbf7a1be..7b1a856c8d 100644
--- a/src/southbridge/sis/sis966/sis966_nic.c
+++ b/src/southbridge/sis/sis966/sis966_nic.c
@@ -34,7 +34,7 @@
 #include "sis966.h"
 
 
-uint8_t	SiS_SiS191_init[6][3]={
+u8	SiS_SiS191_init[6][3]={
 {0x04, 0xFF, 0x07},
 {0x2C, 0xFF, 0x39},
 {0x2D, 0xFF, 0x10},
@@ -50,17 +50,18 @@ uint8_t	SiS_SiS191_init[6][3]={
 #define TRUE            1
 #define FALSE           0
 
-uint16_t MacAddr[3];
+u16 MacAddr[3];
 
 
-void writeApcByte(int addr, uint8_t value)
+static void writeApcByte(int addr, u8 value)
 {
     outb(addr,0x78);
     outb(value,0x79);
 }
-uint8_t readApcByte(int addr)
+
+static u8 readApcByte(int addr)
 {
-    uint8_t value;
+    u8 value;
     outb(addr,0x78);
     value=inb(0x79);
     return(value);
@@ -68,7 +69,7 @@ uint8_t readApcByte(int addr)
 
 static void readApcMacAddr(void)
 {
-    uint8_t i;
+    u8 i;
 
 // enable APC in south bridge sis966 D2F0
 
@@ -93,9 +94,9 @@ static void readApcMacAddr(void)
 
 static void set_apc(struct device *dev)
 {
-    uint16_t addr;
-    uint16_t i;
-    uint8_t   bTmp;
+    u16 addr;
+    u16 i;
+    u8   bTmp;
 
     /* enable APC in south bridge sis966 D2F0 */
     outl(0x80001048,0xcf8);
@@ -104,8 +105,8 @@ static void set_apc(struct device *dev)
     for(i = 0 ; i <3; i++)
     {
        addr=0x9+2*i;
-       writeApcByte(addr,(uint8_t)(MacAddr[i]&0xFF));
-	writeApcByte(addr+1L,(uint8_t)((MacAddr[i]>>8)&0xFF));
+       writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
+	writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
         // printf("%x - ",readMacAddrByte(0x59+i));
     }
 
@@ -135,11 +136,11 @@ static void set_apc(struct device *dev)
 //      Contents of EEPROM word (Reg).
 //-----------------------------------------------------------------------------
 #define LoopNum 200
-static  unsigned long ReadEEprom( struct device *dev,  uint32_t base,  uint32_t Reg)
+static  unsigned long ReadEEprom( struct device *dev,  u32 base,  u32 Reg)
 {
-    uint32_t 	data;
-    uint32_t 	i;
-    uint32_t 	ulValue;
+    u32 	data;
+    u32 	i;
+    u32 	ulValue;
 
 
     ulValue = (0x80 | (0x2 << 8) | (Reg << 10));  //BIT_7
@@ -169,11 +170,11 @@ static  unsigned long ReadEEprom( struct device *dev,  uint32_t base,  uint32_t
     return data;
 }
 
-static int phy_read(uint32_t  base, unsigned phy_addr, unsigned phy_reg)
+static int phy_read(u32  base, unsigned phy_addr, unsigned phy_reg)
 {
-    uint32_t   ulValue;
-    uint32_t   Read_Cmd;
-    uint16_t   usData;
+    u32   ulValue;
+    u32   Read_Cmd;
+    u16   usData;
 
 
 
@@ -203,10 +204,10 @@ static int phy_read(uint32_t  base, unsigned phy_addr, unsigned phy_reg)
 
 // Detect a valid PHY
 // If there exist a valid PHY then return TRUE, else return FALSE
-static int phy_detect(uint32_t base,uint16_t *PhyAddr) //BOOL PHY_Detect()
+static int phy_detect(u32 base,u16 *PhyAddr) //BOOL PHY_Detect()
 {
     int	              bFoundPhy = FALSE;
-    uint16_t		usData;
+    u16		usData;
     int		       PhyAddress = 0;
 
 
@@ -239,17 +240,15 @@ static int phy_detect(uint32_t base,uint16_t *PhyAddr) //BOOL PHY_Detect()
 static void nic_init(struct device *dev)
 {
         int val;
-        uint16_t  PhyAddr;
-        uint32_t base;
+        u16 PhyAddr;
+        u32 base;
         struct resource *res;
 
-
         print_debug("NIC_INIT:---------->\n");
 
-
 //-------------- enable NIC (SiS19x) -------------------------
 {
-        uint8_t  temp8;
+        u8  temp8;
         int i=0;
         while(SiS_SiS191_init[i][0] != 0)
 	{
diff --git a/src/southbridge/sis/sis966/sis966_reset.c b/src/southbridge/sis/sis966/sis966_reset.c
index 614b8eed40..afc592c26b 100644
--- a/src/southbridge/sis/sis966/sis966_reset.c
+++ b/src/southbridge/sis/sis966/sis966_reset.c
@@ -22,6 +22,7 @@
  */
 
 #include <arch/io.h>
+#include <reset.h>
 
 #define PCI_DEV(BUS, DEV, FN) ( \
 	(((BUS) & 0xFFF) << 20) | \
diff --git a/src/southbridge/sis/sis966/sis966_usb2.c b/src/southbridge/sis/sis966/sis966_usb2.c
index 6cb9873070..108cfee894 100644
--- a/src/southbridge/sis/sis966/sis966_usb2.c
+++ b/src/southbridge/sis/sis966/sis966_usb2.c
@@ -36,7 +36,7 @@
 
 extern struct ehci_debug_info dbg_info;
 
-uint8_t	SiS_SiS7002_init[22][3]={
+u8	SiS_SiS7002_init[22][3]={
 {0x04, 0x00, 0x06},
 {0x0D, 0x00, 0x00},
 
@@ -70,14 +70,14 @@ uint8_t	SiS_SiS7002_init[22][3]={
 
 static void usb2_init(struct device *dev)
 {
-        uint8_t *base;
+        u32 base;
         struct resource *res;
 
         print_debug("USB 2.0 INIT:---------->\n");
 
 //-------------- enable USB2.0 (SiS7002) -------------------------
 {
-        uint8_t  temp8;
+        u8  temp8;
         int i=0;
 
         while(SiS_SiS7002_init[i][0] != 0)
@@ -94,8 +94,8 @@ static void usb2_init(struct device *dev)
         if(!res)
                 return;
 
-        base =(uint8_t *) res->base;
-        printk(BIOS_DEBUG, "base = %p\n", base);
+        base = res->base;
+        printk(BIOS_DEBUG, "base = 0x%08x\n", base);
         write32(base+0x20, 0x2);
 //-----------------------------------------------------------
 
diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c
index a7bb9102c4..a33d6cb5f9 100644
--- a/src/southbridge/via/k8t890/k8t890_early_car.c
+++ b/src/southbridge/via/k8t890/k8t890_early_car.c
@@ -113,7 +113,8 @@ u8 k8t890_early_setup_ht(void)
 	return 1;
 }
 
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos) {
+int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
+{
 	
 	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
 	switch (size) {
@@ -133,7 +134,8 @@ int s3_save_nvram_early(u32 dword, int size, int  nvram_pos) {
 	return nvram_pos;
 }
 
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+{
 	switch (size) {
 	case 1:
 		*old_dword &= ~0xff;
diff --git a/src/superio/winbond/w83627hf/w83627hf_early_serial.c b/src/superio/winbond/w83627hf/w83627hf_early_serial.c
index c7ec012694..19734934c0 100644
--- a/src/superio/winbond/w83627hf/w83627hf_early_serial.c
+++ b/src/superio/winbond/w83627hf/w83627hf_early_serial.c
@@ -47,7 +47,7 @@ static void w83627hf_enable_serial(device_t dev, unsigned iobase)
 	pnp_exit_ext_func_mode(dev);
 }
 
-static void w83627hf_set_clksel_48(device_t dev)
+static inline void w83627hf_set_clksel_48(device_t dev)
 {
 	unsigned port = dev >> 8;
 	pnp_enter_ext_func_mode(dev);
diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c
index c5108250b1..53e2a2bddb 100644
--- a/src/superio/winbond/w83697hf/superio.c
+++ b/src/superio/winbond/w83697hf/superio.c
@@ -44,7 +44,7 @@ static void pnp_exit_ext_func_mode(device_t dev)
 static void w83697hf_init(device_t dev)
 {
 	struct superio_winbond_w83697hf_config *conf;
-	struct resource *res0, *res1;
+	struct resource *res0;
 
 	if (!dev->enabled)
 		return;