baytrail: allow ramstage_cache_location() usage in ramstage

To prepare for caching reference code for S3 resume the
ramstage cache needs to be accesible in ramstage as well.

BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.

Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179776
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5012
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

3 files changed, 37 insertions, 13 deletions

diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index e2a949f74b..aff09be238 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -45,6 +45,8 @@ ramstage-y += lpss.c
 ramstage-y += pcie.c
 ramstage-y += sd.c
 ramstage-y += perf_power.c
+ramstage-y += stage_cache.c
+romstage-y += stage_cache.c
 
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 8436c65d17..cb884bd0f1 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -355,19 +355,6 @@ static void *setup_stack_and_mttrs(void)
 	return slot;
 }
 
-struct ramstage_cache *ramstage_cache_location(long *size)
-{
-	char *smm_base;
-	/* 1MiB cache size */
-	const long cache_size = CONFIG_SMM_RESERVED_SIZE;
-
-	/* Ramstage cache lives in TSEG region which is the definition of
-	 * cbmem_top(). */
-	smm_base = cbmem_top();
-	*size = cache_size;
-	return (void *)&smm_base[smm_region_size() - cache_size];
-}
-
 void ramstage_cache_invalid(struct ramstage_cache *cache)
 {
 #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c
new file mode 100644
index 0000000000..3bda56d968
--- /dev/null
+++ b/src/soc/intel/baytrail/stage_cache.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbmem.h>
+#include <ramstage_cache.h>
+#include <baytrail/smm.h>
+
+struct ramstage_cache *ramstage_cache_location(long *size)
+{
+	char *smm_base;
+	/* 1MiB cache size */
+	const long cache_size = CONFIG_SMM_RESERVED_SIZE;
+
+	/* Ramstage cache lives in TSEG region which is the definition of
+	 * cbmem_top(). */
+	smm_base = cbmem_top();
+	*size = cache_size;
+	return (void *)&smm_base[smm_region_size() - cache_size];
+}