X201: Move early nehalem S3 magic to right place.

This MCH magic needs to be done before GPIO.

Now S3 (Suspend-to-RAM) works on X201.

Change-Id: I319e57af52ff01083bfbffbcd883ac5f453320a1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4632
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

3 files changed, 9 insertions, 16 deletions

diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 3edf9fba86..57e1e505a0 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -240,25 +240,19 @@ void main(unsigned long bist)
 	if (bist == 0)
 		enable_lapic();
 
-	/* Force PCIRST# */
-	pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
-	pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, SBR);
-	udelay(200 * 1000);
-	pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
-	pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, 0);
+	nehalem_early_initialization(NEHALEM_MOBILE);
+
+	pch_enable_lpc();
 
 	/* Enable USB Power. We need to do it early for usbdebug to work. */
 	ec_set_bit(0x3b, 4);
 
-	pch_enable_lpc();
-
 	/* Enable GPIOs */
 	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
 	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
 
 	setup_pch_gpios(&x201_gpio_map);
 
-	nehalem_early_initialization(NEHALEM_MOBILE);
 
 	/* This should probably go away. Until now it is required
 	 * and mainboard specific
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index 81bac87c2f..ee8c17a18c 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -166,4 +166,10 @@ void nehalem_early_initialization(int chipset_type)
 	pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, DEFAULT_HECIBAR);
 	pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
 			   PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+	/* Magic for S3 resume. Must be done early.  */
+	if (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) {
+		MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6;
+		MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4;
+	}
 }
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 2a5da1bd74..a855982a35 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -3815,13 +3815,6 @@ void raminit(const int s3resume)
 	unsigned channel, slot, lane, rank;
 	int i;
 	struct raminfo info;
-	if (s3resume) {
-		read_mchbar32(0x1e8);
-		write_mchbar32(0x1e8, 0x6);
-		read_mchbar32(0x1e8);
-		write_mchbar32(0x1e8, 0x4);
-	}
-
 	u8 x2ca8;
 
 	gav(x2ca8 = read_mchbar8(0x2ca8));