mainboard/google/slippy: remove unobtainable mainboard

The slippy board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.

Change-Id: I24fb08d9be35b2367e7aa64520ce5778ab861535
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15902
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

30 files changed, 0 insertions, 2139 deletions

diff --git a/src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex
deleted file mode 100644
index 7b0932743d..0000000000
--- a/src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex
+++ /dev/null
@@ -1,17 +0,0 @@
-# Hynix HMT425S6AFR6A-PBA
-92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
-69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB
-48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42
-20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig
deleted file mode 100644
index 8d078c4764..0000000000
--- a/src/mainboard/google/slippy/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-if BOARD_GOOGLE_SLIPPY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_INTEL_HASWELL
-	select NORTHBRIDGE_INTEL_HASWELL
-	select SOUTHBRIDGE_INTEL_LYNXPOINT
-	select INTEL_LYNXPOINT_LP
-	select BOARD_ROMSIZE_KB_8192
-	select EC_GOOGLE_CHROMEEC
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-	select HAVE_ACPI_RESUME
-	select MMCONF_SUPPORT
-	select HAVE_SMI_HANDLER
-	select MAINBOARD_HAS_CHROMEOS
-	select MAINBOARD_HAS_LPC_TPM
-	select INTEL_DP
-	select INTEL_DDI
-	select INTEL_INT15
-
-config CHROMEOS
-	select CHROMEOS_VBNV_CMOS
-	select LID_SWITCH
-	select EC_SOFTWARE_SYNC
-	select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
-	string
-	default google/slippy
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Slippy"
-
-config MMCONF_BASE_ADDRESS
-	hex
-	default 0xf0000000
-
-config MAX_CPUS
-	int
-	default 8
-
-config VGA_BIOS_FILE
-	string
-	default "pci8086,0166.rom"
-
-config HAVE_IFD_BIN
-	bool
-	default n
-
-config HAVE_ME_BIN
-	bool
-	default n
-
-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "X86 SLIPPY TEST 1717"
-endif
diff --git a/src/mainboard/google/slippy/Kconfig.name b/src/mainboard/google/slippy/Kconfig.name
deleted file mode 100644
index 4892fca2f0..0000000000
--- a/src/mainboard/google/slippy/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_SLIPPY
-	bool "Slippy"
diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc
deleted file mode 100644
index 0068dbd7c3..0000000000
--- a/src/mainboard/google/slippy/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2012 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-
-romstage-y += chromeos.c
-ramstage-y += chromeos.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-## DIMM SPD for on-board memory
-SPD_BIN = $(obj)/spd.bin
-
-# Order of names in SPD_SOURCES is important!
-SPD_SOURCES  = Micron_4KTF25664HZ
-SPD_SOURCES += Hynix_HMT425S6AFR6A
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-
-# Include spd rom data
-$(SPD_BIN): $(SPD_DEPS)
-	for f in $+; \
-	  do for c in $$(cat $$f | grep -v ^#); \
-	    do printf $$(printf '\%o' 0x$$c); \
-	  done; \
-	done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex
deleted file mode 100644
index cbe9e4fbfe..0000000000
--- a/src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex
+++ /dev/null
@@ -1,17 +0,0 @@
-# Micron 4KTF25664HZ-1G6E1
-92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
-69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75
-34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45
-31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/slippy/acpi/chromeos.asl b/src/mainboard/google/slippy/acpi/chromeos.asl
deleted file mode 100644
index 673985fc25..0000000000
--- a/src/mainboard/google/slippy/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button
-	Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/google/slippy/acpi/ec.asl b/src/mainboard/google/slippy/acpi/ec.asl
deleted file mode 100644
index 2b32392df2..0000000000
--- a/src/mainboard/google/slippy/acpi/ec.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include <mainboard/google/slippy/ec.h>
-
-/* ACPI code for EC functions */
-#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl
deleted file mode 100644
index 40658a9839..0000000000
--- a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for IvyBridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, 0, 16 },
-			// Mini-HD Audio		0:3.0
-			Package() { 0x0003ffff, 0, 0, 16 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, 0, 22 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, 0, 16 },
-			Package() { 0x001cffff, 1, 0, 17 },
-			Package() { 0x001cffff, 2, 0, 18 },
-			Package() { 0x001cffff, 3, 0, 19 },
-			// EHCI	  			0:1d.0
-			Package() { 0x001dffff, 0, 0, 19 },
-			// XHCI	  			0:14.0
-			Package() { 0x0014ffff, 0, 0, 18 },
-			// LPC devices			0:1f.0
-			Package() { 0x001fffff, 0, 0, 22 },
-			Package() { 0x001fffff, 1, 0, 18 },
-			Package() { 0x001fffff, 2, 0, 17 },
-			Package() { 0x001fffff, 3, 0, 16 },
-			// Serial IO                    0:15.0
-			Package() { 0x0015ffff, 0, 0, 20 },
-			Package() { 0x0015ffff, 1, 0, 21 },
-			Package() { 0x0015ffff, 2, 0, 21 },
-			Package() { 0x0015ffff, 3, 0, 21 },
-			// SDIO                         0:17.0
-			Package() { 0x0017ffff, 0, 0, 23 },
-		})
-	} Else {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// Mini-HD Audio		0:3.0
-			Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	  			0:1d.0
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			// XHCI	  			0:14.0
-			Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
-			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
-			// Serial IO                    0:15.0
-			Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
-			Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
-			Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
-			Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
-			// SDIO                         0:17.0
-			Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
-		})
-	}
-}
diff --git a/src/mainboard/google/slippy/acpi/mainboard.asl b/src/mainboard/google/slippy/acpi/mainboard.asl
deleted file mode 100644
index 60d9a618ae..0000000000
--- a/src/mainboard/google/slippy/acpi/mainboard.asl
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <mainboard/google/slippy/onboard.h>
-
-Scope (\_SB)
-{
-	Device (LID0)
-	{
-		Name(_HID, EisaId("PNP0C0D"))
-		Method(_LID, 0)
-		{
-			Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
-			Return (\LIDS)
-		}
-	}
-
-	Device (PWRB)
-	{
-		Name(_HID, EisaId("PNP0C0C"))
-	}
-
-	Device (TPAD)
-	{
-		Name (_ADR, 0x0)
-		Name (_UID, 1)
-
-		// Report as a Sleep Button device so Linux will
-		// automatically enable it as a wake source
-		Name (_HID, EisaId("PNP0C0E"))
-
-		Name (_CRS, ResourceTemplate()
-		{
-			Interrupt (ResourceConsumer, Edge, ActiveLow)
-			{
-				BOARD_TRACKPAD_IRQ
-			}
-
-			VendorShort (ADDR)
-			{
-				BOARD_TRACKPAD_I2C_ADDR
-			}
-		})
-
-		Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
-
-		Method (_DSW, 3, NotSerialized)
-		{
-			Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
-
-			If (LEqual (Arg0, 1)) {
-				// Enable GPIO as wake source
-				\_SB.PCI0.LPCB.GWAK (Local0)
-			}
-		}
-	}
-
-	Device (TSCR)
-	{
-		Name (_ADR, 0x0)
-		Name (_UID, 2)
-
-		// Report as a Sleep Button device so Linux will
-		// automatically enable it as a wake source
-		Name (_HID, EisaId("PNP0C0E"))
-
-		Name (_CRS, ResourceTemplate()
-		{
-			Interrupt (ResourceConsumer, Edge, ActiveLow)
-			{
-				BOARD_TOUCHSCREEN_IRQ
-			}
-
-			VendorShort (ADDR)
-			{
-				BOARD_TOUCHSCREEN_I2C_ADDR
-			}
-		})
-
-		Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
-
-		Method (_DSW, 3, NotSerialized)
-		{
-			Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
-
-			If (LEqual (Arg0, 1)) {
-				// Enable GPIO as wake source
-				\_SB.PCI0.LPCB.GWAK (Local0)
-			}
-		}
-	}
-}
diff --git a/src/mainboard/google/slippy/acpi/platform.asl b/src/mainboard/google/slippy/acpi/platform.asl
deleted file mode 100644
index 1bd054da06..0000000000
--- a/src/mainboard/google/slippy/acpi/platform.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
-	APMC, 8,	// APM command
-	APMS, 8		// APM status
-}
-
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
-	DBG0, 8
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
-	Store (Arg0, SMIF)	// SMI Function
-	Store (0, TRP0)		// Generate trap
-	Return (SMIF)		// Return value of SMI handler
-}
-
-/* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
-Method(_PIC, 1)
-{
-	// Remember the OS' IRQ routing choice.
-	Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
-	/* Update AC status */
-	Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0)
-	if (LNotEqual (Local0, \PWRS)) {
-		Store (Local0, \PWRS)
-		Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
-	}
-
-	/* Update LID status */
-	Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0)
-	if (LNotEqual (Local0, \LIDS)) {
-		Store (Local0, \LIDS)
-		Notify (\_SB.LID0, 0x80)
-	}
-
-	Return(Package(){0,0})
-}
diff --git a/src/mainboard/google/slippy/acpi/superio.asl b/src/mainboard/google/slippy/acpi/superio.asl
deleted file mode 100644
index ff0d53400a..0000000000
--- a/src/mainboard/google/slippy/acpi/superio.asl
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include <mainboard/google/slippy/ec.h>
-
-#define SIO_EC_MEMMAP_ENABLE     // EC Memory Map Resources
-#define SIO_EC_HOST_ENABLE       // EC Host Interface Resources
-#define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
-#define SIO_EC_ENABLE_COM1       // Enable Serial Port 1
-
-/* ACPI code for EC SuperIO functions */
-#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/slippy/acpi/thermal.asl b/src/mainboard/google/slippy/acpi/thermal.asl
deleted file mode 100644
index 0aae633cb7..0000000000
--- a/src/mainboard/google/slippy/acpi/thermal.asl
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// Thermal Zone
-
-Scope (\_TZ)
-{
-	ThermalZone (THRM)
-	{
-		Name (_TC1, 0x02)
-		Name (_TC2, 0x05)
-
-		// Thermal zone polling frequency: 10 seconds
-		Name (_TZP, 100)
-
-		// Thermal sampling period for passive cooling: 2 seconds
-		Name (_TSP, 20)
-
-		// Convert from Degrees C to 1/10 Kelvin for ACPI
-		Method (CTOK, 1) {
-			// 10th of Degrees C
-			Multiply (Arg0, 10, Local0)
-
-			// Convert to Kelvin
-			Add (Local0, 2732, Local0)
-
-			Return (Local0)
-		}
-
-		// Threshold for OS to shutdown
-		Method (_CRT, 0, Serialized)
-		{
-			Return (CTOK (\TCRT))
-		}
-
-		// Threshold for passive cooling
-		Method (_PSV, 0, Serialized)
-		{
-			Return (CTOK (\TPSV))
-		}
-
-		// Processors used for passive cooling
-		Method (_PSL, 0, Serialized)
-		{
-			Return (\PPKG ())
-		}
-
-		Method (_TMP, 0, Serialized)
-		{
-			// Get Temperature from TIN# set in NVS
-			Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0)
-
-			// Check for sensor not calibrated
-			If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) {
-				Return (CTOK(0))
-			}
-
-			// Check for sensor not present
-			If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
-				Return (CTOK(0))
-			}
-
-			// Check for sensor not powered
-			If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
-				Return (CTOK(0))
-			}
-
-			// Check for sensor bad reading
-			If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
-				Return (CTOK(0))
-			}
-
-			// Adjust by offset to get Kelvin
-			Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
-
-			// Convert to 1/10 Kelvin
-			Multiply (Local0, 10, Local0)
-			Return (Local0)
-		}
-
-		/* CTDP Down */
-		Method (_AC0) {
-			If (LLessEqual (\FLVL, 0)) {
-				Return (CTOK (\F0OF))
-			} Else {
-				Return (CTOK (\F0ON))
-			}
-		}
-
-		/* CTDP Nominal */
-		Method (_AC1) {
-			If (LLessEqual (\FLVL, 1)) {
-				Return (CTOK (\F1OF))
-			} Else {
-				Return (CTOK (\F1ON))
-			}
-		}
-
-		Name (_AL0, Package () { TDP0 })
-		Name (_AL1, Package () { TDP1 })
-
-		PowerResource (TNP0, 0, 0)
-		{
-			Method (_STA) {
-				If (LLessEqual (\FLVL, 0)) {
-					Return (One)
-				} Else {
-					Return (Zero)
-				}
-			}
-			Method (_ON)  {
-				Store (0, \FLVL)
-				\_SB.PCI0.MCHC.STND ()
-				Notify (\_TZ.THRM, 0x81)
-			}
-			Method (_OFF) {
-				Store (1, \FLVL)
-				\_SB.PCI0.MCHC.STDN ()
-				Notify (\_TZ.THRM, 0x81)
-			}
-		}
-
-		PowerResource (TNP1, 0, 0)
-		{
-			Method (_STA) {
-				If (LLessEqual (\FLVL, 1)) {
-					Return (One)
-				} Else {
-					Return (Zero)
-				}
-			}
-			Method (_ON)  {
-				Store (1, \FLVL)
-				Notify (\_TZ.THRM, 0x81)
-			}
-			Method (_OFF) {
-				Store (1, \FLVL)
-				Notify (\_TZ.THRM, 0x81)
-			}
-		}
-
-		Device (TDP0)
-		{
-			Name (_HID, EISAID ("PNP0C0B"))
-			Name (_UID, 0)
-			Name (_PR0, Package () { TNP0 })
-		}
-
-		Device (TDP1)
-		{
-			Name (_HID, EISAID ("PNP0C0B"))
-			Name (_UID, 1)
-			Name (_PR0, Package () { TNP1 })
-		}
-	}
-}
diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c
deleted file mode 100644
index 68ca066c7f..0000000000
--- a/src/mainboard/google/slippy/acpi_tables.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/msr.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-#include <ec/google/chromeec/ec.h>
-
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
-#include "thermal.h"
-
-static void acpi_update_thermal_table(global_nvs_t *gnvs)
-{
-	gnvs->tmps = CTDP_SENSOR_ID;
-
-	gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF;
-	gnvs->f1on = CTDP_NOMINAL_THRESHOLD_ON;
-
-	gnvs->f0of = CTDP_DOWN_THRESHOLD_OFF;
-	gnvs->f0on = CTDP_DOWN_THRESHOLD_ON;
-
-	gnvs->tcrt = CRITICAL_TEMPERATURE;
-	gnvs->tpsv = PASSIVE_TEMPERATURE;
-	gnvs->tmax = MAX_TEMPERATURE;
-	gnvs->flvl = 1;
-}
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	/* Enable USB ports in S3 */
-	gnvs->s3u0 = 1;
-	gnvs->s3u1 = 1;
-
-	/* Disable USB ports in S5 */
-	gnvs->s5u0 = 0;
-	gnvs->s5u1 = 0;
-
-	/* TPM Present */
-	gnvs->tpmp = 1;
-
-
-#if CONFIG_CHROMEOS
-	gnvs->chromeos.vbt2 = google_ec_running_ro() ?
-		ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
-#endif
-
-	acpi_update_thermal_table(gnvs);
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
diff --git a/src/mainboard/google/slippy/board_info.txt b/src/mainboard/google/slippy/board_info.txt
deleted file mode 100644
index eca915ffc1..0000000000
--- a/src/mainboard/google/slippy/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Category: eval
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c
deleted file mode 100644
index 1659d9cc87..0000000000
--- a/src/mainboard/google/slippy/chromeos.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <bootmode.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/common/gpio.h>
-
-#if CONFIG_EC_GOOGLE_CHROMEEC
-#include "ec.h"
-#include <ec/google/chromeec/ec.h>
-#endif
-
-#ifndef __PRE_RAM__
-#include <boot/coreboot_tables.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	struct lb_gpio chromeos_gpios[] = {
-		{58, ACTIVE_HIGH, 0, "write protect"},
-		{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
-		{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
-		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
-		{-1, ACTIVE_HIGH, 0, "power"},
-		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
-	};
-	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-#endif
-
-int get_lid_switch(void)
-{
-#if CONFIG_EC_GOOGLE_CHROMEEC
-	u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
-
-	return !!(ec_switches & EC_SWITCH_LID_OPEN);
-#else
-	return 0;
-#endif
-}
-
-/* The dev-switch is virtual */
-int get_developer_mode_switch(void)
-{
-	return 0;
-}
-
-/* There are actually two recovery switches. One is the magic keyboard chord,
- * the other is driven by Servo. */
-int get_recovery_mode_switch(void)
-{
-#if CONFIG_EC_GOOGLE_CHROMEEC
-	u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
-	u32 ec_events;
-
-	/* If a switch is set, we don't need to look at events. */
-	if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY))
-		return 1;
-
-	/* Else check if the EC has posted the keyboard recovery event. */
-	ec_events = google_chromeec_get_events_b();
-
-	return !!(ec_events &
-		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-#else
-	return 0;
-#endif
-}
-
-int get_write_protect_state(void)
-{
-	return get_gpio(58);
-}
diff --git a/src/mainboard/google/slippy/chromeos.fmd b/src/mainboard/google/slippy/chromeos.fmd
deleted file mode 100644
index 113fba6e6f..0000000000
--- a/src/mainboard/google/slippy/chromeos.fmd
+++ /dev/null
@@ -1,38 +0,0 @@
-FLASH@0xff800000 0x800000 {
-	SI_ALL@0x0 0x200000 {
-		SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x1ff000
-	}
-	SI_BIOS@0x200000 0x600000 {
-		RW_SECTION_A@0x0 0xf0000 {
-			VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0xdffc0
-			RW_FWID_A@0xeffc0 0x40
-		}
-		RW_SECTION_B@0xf0000 0xf0000 {
-			VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0xdffc0
-			RW_FWID_B@0xeffc0 0x40
-		}
-		RW_MRC_CACHE@0x1e0000 0x10000
-		RW_ELOG@0x1f0000 0x4000
-		RW_SHARED@0x1f4000 0x4000 {
-			SHARED_DATA@0x0 0x2000
-			VBLOCK_DEV@0x2000 0x2000
-		}
-		RW_VPD@0x1f8000 0x2000
-		RW_UNUSED@0x1fa000 0x6000
-		RW_LEGACY(CBFS)@0x200000 0x200000
-		WP_RO@0x400000 0x200000 {
-			RO_VPD@0x0 0x4000
-			RO_UNUSED@0x4000 0xc000
-			RO_SECTION@0x10000 0x1f0000 {
-				FMAP@0x0 0x800
-				RO_FRID@0x800 0x40
-				RO_FRID_PAD@0x840 0x7c0
-				GBB@0x1000 0xef000
-				COREBOOT(CBFS)@0xf0000 0x100000
-			}
-		}
-	}
-}
diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout
deleted file mode 100644
index 2a518e9213..0000000000
--- a/src/mainboard/google/slippy/cmos.layout
+++ /dev/null
@@ -1,110 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-388          4       r       0        reboot_bits
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-392          3       e       5        baud_rate
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-400          1       e       2        hyper_threading
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-409          2       e       7        power_on_after_fail
-#411          5       r       0        unused
-
-# coreboot config options: bootloader
-#Used by ChromeOS:
-416        128       r        0        vbnv
-#544        440       r       0        unused
-
-# SandyBridge MRC Scrambler Seed values
-896         32        r       0        mrc_scrambler_seed
-928         32        r       0        mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-#1000        24       r       0        amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-5     0     115200
-5     1     57600
-5     2     38400
-5     3     19200
-5     4     9600
-5     5     4800
-5     6     2400
-5     7     1200
-6     1     Emergency
-6     2     Alert
-6     3     Critical
-6     4     Error
-6     5     Warning
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
deleted file mode 100644
index 3d4c8c5068..0000000000
--- a/src/mainboard/google/slippy/devicetree.cb
+++ /dev/null
@@ -1,116 +0,0 @@
-chip northbridge/intel/haswell
-	# IGD Displays
-	register "gfx.ndid" = "3"
-	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
-
-	# Enable eDP Hotplug with 6ms pulse
-	register "gpu_dp_d_hotplug" = "0x06"
-
-	# Disable DisplayPort C Hotplug
-	register "gpu_dp_c_hotplug" = "0x00"
-
-	# Enable HDMI Hotplug with 6ms pulse
-	register "gpu_dp_b_hotplug" = "0x06"
-
-	# Set backlight PWM values for eDP
-	register "gpu_cpu_backlight" = "0x00000200"
-	register "gpu_pch_backlight" = "0x04000000"
-
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
-	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
-	register "gpu_panel_power_up_delay" = "400"		# 40ms
-	register "gpu_panel_power_down_delay" = "150"		# 15ms
-	register "gpu_panel_power_backlight_on_delay" = "2100"	# 210ms
-	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
-
-	device cpu_cluster 0 on
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-
-			register "c1_battery" = "2"	# ACPI(C1) = MWAIT(C1E)
-			register "c2_battery" = "3"	# ACPI(C2) = MWAIT(C3)
-			register "c3_battery" = "9"	# ACPI(C3) = MWAIT(C7S)
-
-			register "c1_acpower" = "2"	# ACPI(C1) = MWAIT(C1E)
-			register "c2_acpower" = "3"	# ACPI(C2) = MWAIT(C3)
-			register "c3_acpower" = "9"	# ACPI(C3) = MWAIT(C7S)
-		end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-		device pci 03.0 on end # mini-hd audio
-
-		chip southbridge/intel/lynxpoint
-			register "pirqa_routing" = "0x8b"
-			register "pirqb_routing" = "0x8a"
-			register "pirqc_routing" = "0x8b"
-			register "pirqd_routing" = "0x8b"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x80"
-
-			# EC range is 0x800-0x9ff
-			register "gen1_dec" = "0x00fc0801"
-			register "gen2_dec" = "0x00fc0901"
-
-			# EC_SMI is GPIO34
-			register "alt_gp_smi_en" = "0x0004"
-			register "gpe0_en_1" = "0x00000000"
-			# EC_SCI is GPIO36
-			register "gpe0_en_2" = "0x00000010"
-			register "gpe0_en_3" = "0x00000000"
-			register "gpe0_en_4" = "0x00000000"
-
-			register "ide_legacy_combined" = "0x0"
-			register "sata_ahci" = "0x1"
-			register "sata_port_map" = "0x1"
-
-			register "sio_acpi_mode" = "0"
-			register "sio_i2c0_voltage" = "0" # 3.3V
-			register "sio_i2c1_voltage" = "0" # 3.3V
-
-			device pci 13.0 off end # Smart Sound Audio DSP
-			device pci 14.0 on end # USB3 XHCI
-			device pci 15.0 on end # Serial I/O DMA
-			device pci 15.1 on end # I2C0
-			device pci 15.2 on end # I2C1
-			device pci 15.3 off end # GSPI0
-			device pci 15.4 off end # GSPI1
-			device pci 15.5 off end # UART0
-			device pci 15.6 off end # UART1
-			device pci 16.0 on end # Management Engine Interface 1
-			device pci 16.1 off end # Management Engine Interface 2
-			device pci 16.2 off end # Management Engine IDE-R
-			device pci 16.3 off end # Management Engine KT
-			device pci 17.0 off end # SDIO
-			device pci 19.0 off end # GbE
-			device pci 1b.0 on end # High Definition Audio
-			device pci 1c.0 on end # PCIe Port #1
-			device pci 1c.1 off end # PCIe Port #2
-			device pci 1c.2 off end # PCIe Port #3
-			device pci 1c.3 off end # PCIe Port #4
-			device pci 1c.4 off end # PCIe Port #5
-			device pci 1c.5 off end # PCIe Port #6
-			device pci 1d.0 on end # USB2 EHCI
-			device pci 1e.0 off end # PCI bridge
-			device pci 1f.0 on
-				chip ec/google/chromeec
-					# We only have one init function that
-					# we need to call to initialize the
-					# keyboard part of the EC.
-					device pnp ff.1 on # dummy address
-					end
-				end
-			end # LPC bridge
-			device pci 1f.2 on end # SATA Controller
-			device pci 1f.3 on end # SMBus
-			device pci 1f.6 on end # Thermal
-		end
-	end
-end
diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl
deleted file mode 100644
index 9e5a114938..0000000000
--- a/src/mainboard/google/slippy/dsdt.asl
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define ENABLE_TPM
-
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0
-	"COREv4",	// OEM id
-	"COREBOOT",	// OEM table id
-	0x20110725	// OEM revision
-)
-{
-	// Some generic macros
-	#include "acpi/platform.asl"
-	#include "acpi/mainboard.asl"
-
-	// global NVS and variables
-	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
-
-	// General Purpose Events
-	//#include "acpi/gpe.asl"
-
-	// CPU
-	#include <cpu/intel/haswell/acpi/cpu.asl>
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <northbridge/intel/haswell/acpi/haswell.asl>
-			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
-
-			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-		}
-	}
-
-	// Thermal handler
-	#include "acpi/thermal.asl"
-
-	// Chrome OS specific
-	#include "acpi/chromeos.asl"
-	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
-
-	// Chipset specific sleep states
-	#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
-}
diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c
deleted file mode 100644
index c011f33d60..0000000000
--- a/src/mainboard/google/slippy/ec.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <types.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include "ec.h"
-
-void mainboard_ec_init(void)
-{
-	printk(BIOS_DEBUG, "mainboard_ec_init\n");
-	post_code(0xf0);
-
-	/* Restore SCI event mask on resume. */
-	if (acpi_is_wakeup_s3()) {
-		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
-					   MAINBOARD_EC_S3_WAKE_EVENTS);
-
-		/* Disable SMI and wake events */
-		google_chromeec_set_smi_mask(0);
-
-		/* Clear pending events */
-		while (google_chromeec_get_event() != 0);
-		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
-	} else {
-		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
-					   MAINBOARD_EC_S5_WAKE_EVENTS);
-	}
-
-	/* Clear wake events, these are enabled on entry to sleep */
-	google_chromeec_set_wake_mask(0);
-
-	post_code(0xf1);
-}
diff --git a/src/mainboard/google/slippy/ec.h b/src/mainboard/google/slippy/ec.h
deleted file mode 100644
index 89630b2660..0000000000
--- a/src/mainboard/google/slippy/ec.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_EC_H
-#define MAINBOARD_EC_H
-
-#include <ec/google/chromeec/ec_commands.h>
-
-#define EC_SCI_GPI  36   /* GPIO36 is EC_SCI# */
-#define EC_SMI_GPI  34   /* GPIO34 is EC_SMI# */
-
-#define MAINBOARD_EC_SCI_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD)  |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
-
-#define MAINBOARD_EC_SMI_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
-
-/* EC can wake from S5 with lid or power button */
-#define MAINBOARD_EC_S5_WAKE_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/* EC can wake from S3 with lid or power button or key press */
-#define MAINBOARD_EC_S3_WAKE_EVENTS \
-	(MAINBOARD_EC_S5_WAKE_EVENTS |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
-
-/* Log EC wake events plus EC shutdown events */
-#define MAINBOARD_EC_LOG_EVENTS \
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
-
-#ifndef __ACPI__
-extern void mainboard_ec_init(void);
-#endif
-
-#endif
diff --git a/src/mainboard/google/slippy/fadt.c b/src/mainboard/google/slippy/fadt.c
deleted file mode 100644
index 2452ac2a36..0000000000
--- a/src/mainboard/google/slippy/fadt.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = get_pmbase();
-
-	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
-	memcpy(header->signature, "FACP", 4);
-	header->length = sizeof(acpi_fadt_t);
-	header->revision = 3;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 1;
-
-	fadt->firmware_ctrl = (unsigned long) facs;
-	fadt->dsdt = (unsigned long) dsdt;
-	fadt->model = 1;
-	fadt->preferred_pm_profile = PM_MOBILE;
-
-	fadt->sci_int = 0x9;
-	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
-	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0;
-
-	fadt->pm1a_evt_blk = pmbase;
-	fadt->pm1b_evt_blk = 0x0;
-	fadt->pm1a_cnt_blk = pmbase + 0x4;
-	fadt->pm1b_cnt_blk = 0x0;
-	fadt->pm2_cnt_blk = pmbase + 0x50;
-	fadt->pm_tmr_blk = pmbase + 0x8;
-	fadt->gpe0_blk = pmbase + 0x80;
-	fadt->gpe1_blk = 0;
-
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 32;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-	fadt->cst_cnt = 0;
-	fadt->p_lvl2_lat = 1;
-	fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 0;
-	fadt->day_alrm = 0xd;
-	fadt->mon_alrm = 0x00;
-	fadt->century = 0x00;
-	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
-
-	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
-			ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
-			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
-	fadt->reset_reg.space_id = 1;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0;
-
-	fadt->reset_value = 6;
-	fadt->x_firmware_ctl_l = (unsigned long)facs;
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (unsigned long)dsdt;
-	fadt->x_dsdt_h = 0;
-
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = pmbase;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 0;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 0;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 8;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	fadt->x_gpe0_blk.space_id = 0;
-	fadt->x_gpe0_blk.bit_width = 0;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = 0;
-	fadt->x_gpe0_blk.addrh = 0x0;
-
-	fadt->x_gpe1_blk.space_id = 1;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0x0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum =
-	    acpi_checksum((void *) fadt, header->length);
-}
diff --git a/src/mainboard/google/slippy/gpio.h b/src/mainboard/google/slippy/gpio.h
deleted file mode 100644
index 7d99715957..0000000000
--- a/src/mainboard/google/slippy/gpio.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef SLIPPY_GPIO_H
-#define SLIPPY_GPIO_H
-
-struct pch_lp_gpio_map;
-
-const struct pch_lp_gpio_map mainboard_gpio_map[] = {
-	LP_GPIO_UNUSED,        /* 0: UNUSED */
-	LP_GPIO_UNUSED,        /* 1: UNUSED */
-	LP_GPIO_UNUSED,        /* 2: UNUSED */
-	LP_GPIO_UNUSED,        /* 3: UNUSED */
-	LP_GPIO_NATIVE,        /* 4: NATIVE: I2C0_SDA_GPIO4 */
-	LP_GPIO_NATIVE,        /* 5: NATIVE: I2C0_SCL_GPIO5 */
-	LP_GPIO_NATIVE,        /* 6: NATIVE: I2C1_SDA_GPIO6 */
-	LP_GPIO_NATIVE,        /* 7: NATIVE: I2C1_SCL_GPIO7 */
-	LP_GPIO_ACPI_SCI,      /* 8: LTE_WAKE_L_Q */
-	LP_GPIO_INPUT,         /* 9: RAM_ID1 */
-	LP_GPIO_ACPI_SCI,      /* 10: WLAN_WAKE_L_Q */
-	LP_GPIO_UNUSED,        /* 11: UNUSED */
-	LP_GPIO_INPUT_INVERT,  /* 12: TRACKPAD_INT_L (WAKE) */
-	LP_GPIO_INPUT,         /* 13: RAM_ID0 */
-	LP_GPIO_INPUT,         /* 14: EC_IN_RW */
-	LP_GPIO_UNUSED,        /* 15: UNUSED (STRAP) */
-	LP_GPIO_OUT_LOW,       /* 16: PCH_SSD_12_EN (iSSD VDDC) */
-	LP_GPIO_OUT_LOW,       /* 17: PCH_SSD_18_EN (iSSD VCCQ) */
-	LP_GPIO_NATIVE,        /* 18: PCIE_CLKREQ_WLAN# */
-	LP_GPIO_UNUSED,        /* 19: UNUSED */
-	LP_GPIO_UNUSED,        /* 20: UNUSED */
-	LP_GPIO_UNUSED,        /* 21: UNUSED */
-	LP_GPIO_UNUSED,        /* 22: UNUSED */
-	LP_GPIO_UNUSED,        /* 23: UNUSED */
-	LP_GPIO_UNUSED,        /* 24: UNUSED */
-	LP_GPIO_INPUT_INVERT,  /* 25: TOUCH_INT_L (WAKE) */
-	LP_GPIO_UNUSED,        /* 26: UNUSED */
-	LP_GPIO_UNUSED,        /* 27: UNUSED */
-	LP_GPIO_UNUSED,        /* 28: UNUSED */
-	LP_GPIO_UNUSED,        /* 29: UNUSED */
-	LP_GPIO_NATIVE,        /* 30: NATIVE: PCH_SUSWARN_L */
-	LP_GPIO_NATIVE,        /* 31: NATIVE: ACPRESENT */
-	LP_GPIO_NATIVE,        /* 32: NATIVE: LPC_CLKRUN_L */
-	LP_GPIO_NATIVE,        /* 33: NATIVE: DEVSLP0 */
-	LP_GPIO_ACPI_SMI,      /* 34: EC_SMI_L */
-	LP_GPIO_ACPI_SMI,      /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
-	LP_GPIO_ACPI_SCI,      /* 36: EC_SCI_L */
-	LP_GPIO_UNUSED,        /* 37: UNUSED */
-	LP_GPIO_UNUSED,        /* 38: UNUSED */
-	LP_GPIO_UNUSED,        /* 39: UNUSED */
-	LP_GPIO_NATIVE,        /* 40: NATIVE: USB_OC0# */
-	LP_GPIO_UNUSED,        /* 41: UNUSED */
-	LP_GPIO_NATIVE,        /* 42: NATIVE: USB_OC2# */
-	LP_GPIO_UNUSED,        /* 43: UNUSED */
-	LP_GPIO_OUT_LOW,       /* 44: PP3300_SSD_EN (iSSD VCC_FLASH) */
-	LP_GPIO_OUT_HIGH,      /* 45: PP3300_CODEC_EN */
-	LP_GPIO_OUT_HIGH,      /* 46: WLAN_DISABLE_L */
-	LP_GPIO_INPUT,         /* 47: RAM_ID2 */
-	LP_GPIO_UNUSED,        /* 48: UNUSED */
-	LP_GPIO_OUT_LOW,       /* 49: PP3300_SSD_IO_EN (iSSD VCC_IO) */
-	LP_GPIO_UNUSED,        /* 50: UNUSED */
-	LP_GPIO_INPUT,         /* 51: ALS_INT_L */
-	LP_GPIO_INPUT,         /* 52: SIM_DET */
-	LP_GPIO_PIRQ,          /* 53: TRACKPAD_INT_DX (PIRQV) */
-	LP_GPIO_PIRQ,          /* 54: TOUCH_INT_L_DX (PIRQW) */
-	LP_GPIO_UNUSED,        /* 55: UNUSED */
-	LP_GPIO_UNUSED,        /* 56: UNUSED */
-	LP_GPIO_OUT_HIGH,      /* 57: PP3300_CCD_EN */
-	LP_GPIO_INPUT,         /* 58: PCH_SPI_WP_D */
-	LP_GPIO_OUT_HIGH,      /* 59: LTE_DISABLE_L */
-	LP_GPIO_NATIVE,        /* 60: NATIVE: SML0ALERT */
-	LP_GPIO_NATIVE,        /* 61: NATIVE: PCH_SUS_STAT */
-	LP_GPIO_NATIVE,        /* 62: NATIVE: PCH_SUS_CLK */
-	LP_GPIO_NATIVE,        /* 63: NATIVE: PCH_SLP_S5_L */
-	LP_GPIO_UNUSED,        /* 64: UNUSED */
-	LP_GPIO_UNUSED,        /* 65: UNUSED */
-	LP_GPIO_UNUSED,        /* 66: UNUSED */
-	LP_GPIO_UNUSED,        /* 67: UNUSED */
-	LP_GPIO_UNUSED,        /* 68: UNUSED */
-	LP_GPIO_UNUSED,        /* 69: UNUSED */
-	LP_GPIO_UNUSED,        /* 70: UNUSED */
-	LP_GPIO_NATIVE,        /* 71: NATIVE: MODPHY_EN */
-	LP_GPIO_NATIVE,        /* 72: NATIVE: PCH_BATLOW# */
-	LP_GPIO_NATIVE,        /* 73: NATIVE: SMB1ALERT# */
-	LP_GPIO_NATIVE,        /* 74: NATIVE: SMB_ME1_DAT */
-	LP_GPIO_NATIVE,        /* 75: NATIVE: SMB_ME1_CLK */
-	LP_GPIO_UNUSED,        /* 76: UNUSED */
-	LP_GPIO_UNUSED,        /* 77: UNUSED */
-	LP_GPIO_UNUSED,        /* 78: UNUSED */
-	LP_GPIO_UNUSED,        /* 79: UNUSED */
-	LP_GPIO_UNUSED,        /* 80: UNUSED */
-	LP_GPIO_NATIVE,        /* 81: NATIVE: SPKR */
-	LP_GPIO_NATIVE,        /* 82: NATIVE: EC_RCIN_L */
-	LP_GPIO_UNUSED,        /* 83: UNUSED */
-	LP_GPIO_UNUSED,        /* 84: UNUSED */
-	LP_GPIO_UNUSED,        /* 85: UNUSED */
-	LP_GPIO_UNUSED,        /* 86: UNUSED (STRAP) */
-	LP_GPIO_UNUSED,        /* 87: UNUSED */
-	LP_GPIO_UNUSED,        /* 88: UNUSED */
-	LP_GPIO_UNUSED,        /* 89: UNUSED */
-	LP_GPIO_UNUSED,        /* 90: UNUSED */
-	LP_GPIO_UNUSED,        /* 91: UNUSED */
-	LP_GPIO_UNUSED,        /* 92: UNUSED */
-	LP_GPIO_UNUSED,        /* 93: UNUSED */
-	LP_GPIO_UNUSED,        /* 94: UNUSED */
-	LP_GPIO_END
-};
-
-#endif
diff --git a/src/mainboard/google/slippy/hda_verb.c b/src/mainboard/google/slippy/hda_verb.c
deleted file mode 100644
index bb29d29259..0000000000
--- a/src/mainboard/google/slippy/hda_verb.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	0x10ec0283,	// Codec Vendor / Device ID: Realtek ALC283
-	0x10ec0283,	// Subsystem ID
-	0x0000000c,	// Number of jacks (NID entries)
-
-	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
-	AZALIA_SUBVENDOR(0x0, 0x10ec0283),
-
-	/* Pin Widget Verb Table */
-
-	/* Pin Complex (NID 0x12) DMIC - interior mobile lid */
-	AZALIA_PIN_CFG(0x0, 0x12, 0xb7a61010),
-
-	/* Pin Complex (NID 0x14) SPKR-OUT PORTD */
-	// group 1, front left/right
-	// no connector, no jack detect
-	// speaker out, analog
-	// fixed function, internal
-	AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
-
-	/* Pin Complex (NID 0x17)  */
-	AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
-
-	/* Pin Complex (NID 0x18)  MIC1 PORTB */
-	// group 1, cap 1
-	// black, jack detect
-	// mic in, analog
-	// connector, left panel
-	AZALIA_PIN_CFG(0x0, 0x19, 0x03a71011),
-
-	/* Pin Complex (NID 0x19)  MIC2 PORTF */
-	AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
-
-	/* Pin Complex (NID 0x1A)  LINE1 PORTC */
-	AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
-
-	/* Pin Complex (NID 0x1B)  LINE2 PORTE */
-	AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
-
-	/* Pin Complex (NID 0x1d)  PCBeep */
-	// eapd low on ex-amp, laptop, custom enable
-	// mute spkr on hpout
-	// pcbeep en able, checksum
-	// no physical, internal
-	AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d),
-
-	/* Pin Complex (NID 0x1E)  SPDIF-OUT */
-	AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
-
-	/* Pin Complex (NID 0x21) HPOUT PORT-I */
-	// group1,
-	// black, jack detect
-	// HPOut, 1/8 stereo
-	// connector, left panel
-	AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f),
-
-	/* Undocumented settings from Realtek (needed for beep_gen) */
-	/* Widget node 0x20 */
-	0x02050010,
-	0x02040c20,
-	0x0205001b,
-	0x0204081b,
-};
-
-const u32 pc_beep_verbs[] = {
-	0x00170500,	/* power up everything (codec, dac, adc, mixers)  */
-	0x01470740,	/* enable speaker out */
-	0x01470c02,	/* set speaker EAPD pin */
-	0x0143b01f,	/* unmute speaker */
-	0x00c37100,	/* unmute mixer nid 0xc input 1 */
-	0x00b37410,	/* unmute mixer nid 0xb beep input and set volume */
-};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c
deleted file mode 100644
index b9ce50eba9..0000000000
--- a/src/mainboard/google/slippy/mainboard.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <smbios.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#include <drivers/intel/gma/int15.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include "ec.h"
-#include "onboard.h"
-
-void mainboard_suspend_resume(void)
-{
-	/* Call SMM finalize() handlers before resume */
-	outb(0xcb, 0xb2);
-}
-
-
-
-static void mainboard_init(device_t dev)
-{
-	mainboard_ec_init();
-}
-
-static int mainboard_smbios_data(device_t dev, int *handle,
-				 unsigned long *current)
-{
-	int len = 0;
-
-	len += smbios_write_type41(
-		current, handle,
-		BOARD_LIGHTSENSOR_NAME,		/* name */
-		BOARD_LIGHTSENSOR_IRQ,		/* instance */
-		BOARD_LIGHTSENSOR_I2C_BUS,	/* segment */
-		BOARD_LIGHTSENSOR_I2C_ADDR,	/* bus */
-		0,				/* device */
-		0);				/* function */
-
-	len += smbios_write_type41(
-		current, handle,
-		BOARD_TRACKPAD_NAME,		/* name */
-		BOARD_TRACKPAD_IRQ,		/* instance */
-		BOARD_TRACKPAD_I2C_BUS,		/* segment */
-		BOARD_TRACKPAD_I2C_ADDR,	/* bus */
-		0,				/* device */
-		0);				/* function */
-
-	len += smbios_write_type41(
-		current, handle,
-		BOARD_TOUCHSCREEN_NAME,		/* name */
-		BOARD_TOUCHSCREEN_IRQ,		/* instance */
-		BOARD_TOUCHSCREEN_I2C_BUS,	/* segment */
-		BOARD_TOUCHSCREEN_I2C_ADDR,	/* bus */
-		0,				/* device */
-		0);				/* function */
-
-	return len;
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
-
-static void mainboard_enable(device_t dev)
-{
-	dev->ops->init = mainboard_init;
-	dev->ops->get_smbios_data = mainboard_smbios_data;
-	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/google/slippy/mainboard.h b/src/mainboard/google/slippy/mainboard.h
deleted file mode 100644
index 6329a27805..0000000000
--- a/src/mainboard/google/slippy/mainboard.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright 2013 Google Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; version 2 of the License.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __MAINBOARD_H_
-#define __MAINBOARD_H_
-void mainboard_train_link(struct intel_dp *intel_dp);
-void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
-
-#endif
diff --git a/src/mainboard/google/slippy/onboard.h b/src/mainboard/google/slippy/onboard.h
deleted file mode 100644
index 36a9195895..0000000000
--- a/src/mainboard/google/slippy/onboard.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef ONBOARD_H
-#define ONBOARD_H
-
-#define BOARD_LIGHTSENSOR_NAME		"lightsensor"
-#define BOARD_LIGHTSENSOR_IRQ		51	/* PIRQT */
-#define BOARD_LIGHTSENSOR_I2C_BUS	2	/* I2C1 */
-#define BOARD_LIGHTSENSOR_I2C_ADDR	0x44
-
-#define BOARD_TRACKPAD_NAME		"trackpad"
-#define BOARD_TRACKPAD_IRQ		37	/* PIRQV */
-#define BOARD_TRACKPAD_WAKE_GPIO	12	/* GPIO12 */
-#define BOARD_TRACKPAD_I2C_BUS		1	/* I2C0 */
-#define BOARD_TRACKPAD_I2C_ADDR		0x67
-
-#define BOARD_TOUCHSCREEN_NAME		"touchscreen"
-#define BOARD_TOUCHSCREEN_IRQ		38	/* PIRQW */
-#define BOARD_TOUCHSCREEN_WAKE_GPIO	25	/* GPIO25 */
-#define BOARD_TOUCHSCREEN_I2C_BUS	2	/* I2C1 */
-#define BOARD_TOUCHSCREEN_I2C_ADDR	0x4a
-
-#endif
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
deleted file mode 100644
index a4cc7ece0d..0000000000
--- a/src/mainboard/google/slippy/romstage.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <cpu/intel/haswell/haswell.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <northbridge/intel/haswell/raminit.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
-#include "gpio.h"
-
-const struct rcba_config_instruction rcba_config[] = {
-
-	/*
-	 *             GFX    INTA -> PIRQA (MSI)
-	 * D28IP_P1IP  PCIE   INTA -> PIRQA
-	 * D29IP_E1P   EHCI   INTA -> PIRQD
-	 * D20IP_XHCI  XHCI   INTA -> PIRQC (MSI)
-	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
-	 * D31IP_SMIP  SMBUS  INTB -> PIRQG
-	 * D31IP_TTIP  THRT   INTC -> PIRQA
-	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
-	 */
-
-	/* Device interrupt pin register (board specific) */
-	RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
-			(INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
-	RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
-	RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
-			(INTB << D28IP_P4IP)),
-	RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
-	RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
-	RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
-	RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
-
-	/* Device interrupt route registers */
-	RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
-	RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
-	RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
-	RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
-	RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
-	RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
-	RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
-	RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
-
-	/* Disable unused devices (board specific) */
-	RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
-
-	RCBA_END_CONFIG,
-};
-
-/* Copy SPD data for on-board memory */
-static void copy_spd(struct pei_data *peid)
-{
-	const int gpio_vector[] = {13, 9, 47, -1};
-	int spd_index = get_gpios(gpio_vector);
-	char *spd_file;
-	size_t spd_file_len;
-
-	printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
-	spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
-						&spd_file_len);
-	if (!spd_file)
-		die("SPD data not found.");
-
-	if (spd_file_len <
-	    ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
-		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
-		spd_index = 0;
-	}
-
-	if (spd_file_len < sizeof(peid->spd_data[0]))
-		die("Missing SPD data.");
-
-	memcpy(peid->spd_data[0],
-	       spd_file +
-	       spd_index * sizeof(peid->spd_data[0]),
-	       sizeof(peid->spd_data[0]));
-}
-
-/*
- * Power Sequencing for SanDisk i100/i110 SSD
- *
- * Must be sequenced in this order with specified timing.
- *
- * 1. VCC_IO    : 30us - 100ms
- * 2. VCC_FLASH : 70us - 10ms
- * 3. VCCQ      : 70us - 10ms
- * 4. VDDC      : 30us - 100ms
- *
- * There is no feedback to know if the voltage has stabilized
- * so this implementation will use the max ramp times.  That
- * means it adds significantly to the boot time.
- */
-static void issd_power_sequence(void)
-{
-	struct gpio_seq {
-		int gpio;
-		int wait_ms;
-	} issd_gpio_seq[] = {
-		{ 49, 100 },	/* VCC_IO:    GPIO 49, wait 100ms */
-		{ 44, 10 },	/* VCC_FLASH: GPIO 44, wait 10ms */
-		{ 17, 10 },	/* VCCQ:      GPIO 17, wait 10ms */
-		{ 16, 100 },	/* VDDC:      GPIO 16, wait 100ms */
-	};
-	int step;
-
-	for (step = 0; step < ARRAY_SIZE(issd_gpio_seq); step++) {
-		set_gpio(issd_gpio_seq[step].gpio, 1);
-		udelay(issd_gpio_seq[step].wait_ms * 1000);
-	}
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
-	struct pei_data pei_data = {
-		.pei_version = PEI_VERSION,
-		.mchbar = (uintptr_t)DEFAULT_MCHBAR,
-		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
-		.epbar = DEFAULT_EPBAR,
-		.pciexbar = DEFAULT_PCIEXBAR,
-		.smbusbar = SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_ADDR,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.temp_mmio_base = 0xfed08000,
-		.system_type = 5, /* ULT */
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
-		.ec_present = 1,
-		// 0 = leave channel enabled
-		// 1 = disable dimm 0 on channel
-		// 2 = disable dimm 1 on channel
-		// 3 = disable dimm 0+1 on channel
-		.dimm_channel0_disabled = 2,
-		.dimm_channel1_disabled = 2,
-		.max_ddr3_freq = 1600,
-		.usb_xhci_on_resume = 1,
-		.usb2_ports = {
-			/* Length, Enable, OCn#, Location */
-			{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
-			  USB_PORT_MINI_PCIE },
-			{ 0x0040, 1, 0,               /* P1: Port A, CN10 */
-			  USB_PORT_BACK_PANEL },
-			{ 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
-			  USB_PORT_INTERNAL },
-			{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
-			  USB_PORT_MINI_PCIE },
-			{ 0x0040, 1, 2,               /* P4: Port B, CN6  */
-			  USB_PORT_BACK_PANEL },
-			{ 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
-			  USB_PORT_SKIP },
-			{ 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
-			  USB_PORT_FLEX },
-			{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
-			  USB_PORT_SKIP },
-		},
-		.usb3_ports = {
-			/* Enable, OCn# */
-			{ 1, 0               }, /* P1; Port A, CN10 */
-			{ 1, 2               }, /* P2; Port B, CN6  */
-			{ 0, USB_OC_PIN_SKIP }, /* P3; */
-			{ 0, USB_OC_PIN_SKIP }, /* P4; */
-		},
-	};
-
-	struct romstage_params romstage_params = {
-		.pei_data = &pei_data,
-		.gpio_map = &mainboard_gpio_map,
-		.rcba_config = &rcba_config[0],
-		.bist = bist,
-		.copy_spd = copy_spd,
-	};
-
-	/* Call into the real romstage main with this board's attributes. */
-	romstage_common(&romstage_params);
-
-	/* Power sequence the iSSD module */
-	issd_power_sequence();
-}
diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c
deleted file mode 100644
index 9cd0cd2a06..0000000000
--- a/src/mainboard/google/slippy/smihandler.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/me.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <cpu/intel/haswell/haswell.h>
-#include <elog.h>
-
-/* Include EC functions */
-#include <ec/google/chromeec/ec.h>
-#include "ec.h"
-
-static u8 mainboard_smi_ec(void)
-{
-	u8 cmd = google_chromeec_get_event();
-	u32 pm1_cnt;
-
-#if CONFIG_ELOG_GSMI
-	/* Log this event */
-	if (cmd)
-		elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
-#endif
-
-	switch (cmd) {
-	case EC_HOST_EVENT_LID_CLOSED:
-		printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
-
-		/* Go to S5 */
-		pm1_cnt = inl(get_pmbase() + PM1_CNT);
-		pm1_cnt |= (0xf << 10);
-		outl(pm1_cnt, get_pmbase() + PM1_CNT);
-		break;
-	}
-
-	return cmd;
-}
-
-/* gpi_sts is GPIO 47:32 */
-void mainboard_smi_gpi(u32 gpi_sts)
-{
-	if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
-		/* Process all pending events */
-		while (mainboard_smi_ec() != 0);
-	}
-}
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
-	/* Disable USB charging if required */
-	switch (slp_typ) {
-	case ACPI_S3:
-		if (smm_get_gnvs()->s3u0 == 0)
-			google_chromeec_set_usb_charge_mode(
-				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s3u1 == 0)
-			google_chromeec_set_usb_charge_mode(
-				1, USB_CHARGE_MODE_DISABLED);
-		/* Enable wake events */
-		google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
-		break;
-	case ACPI_S5:
-		if (smm_get_gnvs()->s5u0 == 0)
-			google_chromeec_set_usb_charge_mode(
-				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s5u1 == 0)
-			google_chromeec_set_usb_charge_mode(
-				1, USB_CHARGE_MODE_DISABLED);
-		/* Enable wake events */
-		google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
-		break;
-	}
-
-	/* Disable SCI and SMI events */
-	google_chromeec_set_smi_mask(0);
-	google_chromeec_set_sci_mask(0);
-
-	/* Clear pending events that may trigger immediate wake */
-	while (google_chromeec_get_event() != 0);
-}
-
-
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 apmc)
-{
-	switch (apmc) {
-	case APM_CNT_FINALIZE:
-		if (mainboard_finalized) {
-			printk(BIOS_DEBUG, "SMI#: Already finalized\n");
-			return 0;
-		}
-
-		intel_pch_finalize_smm();
-		intel_northbridge_haswell_finalize_smm();
-		intel_cpu_haswell_finalize_smm();
-
-		mainboard_finalized = 1;
-		break;
-	case APM_CNT_ACPI_ENABLE:
-		google_chromeec_set_smi_mask(0);
-		/* Clear all pending events */
-		while (google_chromeec_get_event() != 0);
-		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
-		break;
-	case APM_CNT_ACPI_DISABLE:
-		google_chromeec_set_sci_mask(0);
-		/* Clear all pending events */
-		while (google_chromeec_get_event() != 0);
-		google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
-		break;
-	}
-	return 0;
-}
diff --git a/src/mainboard/google/slippy/thermal.h b/src/mainboard/google/slippy/thermal.h
deleted file mode 100644
index b471ee1582..0000000000
--- a/src/mainboard/google/slippy/thermal.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef THERMAL_H
-#define THERMAL_H
-
-/* Config TDP Sensor ID */
-#define CTDP_SENSOR_ID			0 /* PECI */
-
-/* Config TDP Nominal */
-#define CTDP_NOMINAL_THRESHOLD_OFF	0
-#define CTDP_NOMINAL_THRESHOLD_ON	0
-
-/* Config TDP Down */
-#define CTDP_DOWN_THRESHOLD_OFF		80
-#define CTDP_DOWN_THRESHOLD_ON		90
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE		104
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE		100
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE			105
-
-#endif