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authorGabe Black <gabeblack@google.com>2013-07-24 06:18:20 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 10:49:08 +0100
commit980180962a1855220de08779fa4697c78757614a (patch)
tree2d3034180965ee9dd6a2a145904249470d02b81a /src
parente13680bdd04f4d2128f024123784a9131f76faad (diff)
pit: Bump the EC SPI bus speed up to 5 MHz
That speed is used with U-Boot instead of the more conservative 500 KHz. Change-Id: Ie9d79db3b52b88c1f3bfec1745634ae6bdc9f4ee Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63193 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4386 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/pit/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index 7ead3c9353..b582f3e19d 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -126,7 +126,7 @@ static void setup_ec(void)
{
/* SPI2 (EC) is slower and needs to work in half-duplex mode with
* single byte bus width. */
- clock_set_rate(PERIPH_ID_SPI2, 500000);
+ clock_set_rate(PERIPH_ID_SPI2, 5000000);
exynos_pinmux_spi2();
}