diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-06-15 17:22:02 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-06-17 20:54:32 +0000 |
| commit | 5edbb1c5d917ae27aa8c869a92f3f8750dea9845 (patch) | |
| tree | 6d4a891ced5ea77980a865b1e6b89ec6a8fb3f15 /src | |
| parent | 3cd3cb6f33cbbd18f9acac01ca5008e2dfb76242 (diff) | |
Revert "soc/amd/picasso: Reconfigure SPI speeds after FSP-S has run"
This reverts commit d5f1e0f9734273f79ebd313bb6a17eda04c22c11.
Reason for revert: FSP-S is now fixed to not touch the SPI
configuration registers. Thus, coreboot does not need to reconfigure
SPI after FSP-S has run.
BUG=b:153506142
TEST=Verified that SPI configuration registers look the same before
and after FSP-S has run. em100 works fine without any additional
changes in coreboot to reconfigure SPI.
Change-Id: I4832e62e0331aa39abe0cca7725915262bb2cf83
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/picasso/chip.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index f703a0f7de..2e5fae58e5 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/spi.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -165,13 +164,6 @@ static void soc_init(void *chip_info) fsp_silicon_init(acpi_is_wakeup_s3()); - /* - * TODO(furquan): Get rid of this once FSP is fixed to not touch SPI - * registers(b/153506142). Currently, FSP-S reconfigures SPI frequency causing em100 to - * stop working. Thus, reconfigure SPI speeds here. - */ - fch_spi_config_modes(); - data_fabric_set_mmio_np(); southbridge_init(chip_info); } |