diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-07-07 19:08:44 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-07-24 12:04:26 +0000 |
| commit | 57dd0733699e5994ac3481cb4913ae5cea8ac857 (patch) | |
| tree | 1ab3269ae38308f50dbdd98b915f4c94ba1b6593 /src | |
| parent | 4966a8c136eb12a0a3dc15a531d71eafb191fdf0 (diff) | |
google/sentry: Add as a variant of glados
Add google/sentry (Lenovo Thinkpad 13 Chromebook) as a variant of
glados Skylake reference board:
- add sentry-specific DPTF, EC config, GPIO config, Kconfig,
NHLT config, PEI data, VBT, SPD data, and devicetree
- add sentry-specific GPIO determination of which audio codec
is present
Adapted from Chromium branch firmware-glados-7820.B, commit
b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX]
Test: build/boot google/sentry, verify correct functionality
Change-Id: I783422aedac8b7fc52098eebd05b2061a1011b60
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27418
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
15 files changed, 907 insertions, 2 deletions
diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 99e538f5df..8ff5472541 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -39,6 +39,7 @@ config MAINBOARD_PART_NUMBER default "Chell" if BOARD_GOOGLE_CHELL default "Glados" if BOARD_GOOGLE_GLADOS default "Lars" if BOARD_GOOGLE_LARS + default "Sentry" if BOARD_GOOGLE_SENTRY config MAINBOARD_FAMILY string @@ -49,12 +50,14 @@ config VARIANT_DIR default "chell" if BOARD_GOOGLE_CHELL default "glados" if BOARD_GOOGLE_GLADOS default "lars" if BOARD_GOOGLE_LARS + default "sentry" if BOARD_GOOGLE_SENTRY config DEVICETREE string default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS default "variants/lars/devicetree.cb" if BOARD_GOOGLE_LARS + default "variants/sentry/devicetree.cb" if BOARD_GOOGLE_SENTRY config MAX_CPUS int @@ -87,4 +90,5 @@ config GBB_HWID default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS default "LARS TEST 5001" if BOARD_GOOGLE_LARS + default "SENTRY TEST 6297" if BOARD_GOOGLE_SENTRY endif diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name index 074d9c35d6..6ad8b191c2 100644 --- a/src/mainboard/google/glados/Kconfig.name +++ b/src/mainboard/google/glados/Kconfig.name @@ -17,3 +17,11 @@ config BOARD_GOOGLE_LARS select DRIVERS_GENERIC_MAX98357A select EXCLUDE_NATIVE_SD_INTERFACE select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_SENTRY + bool "-> Sentry (Lenovo Thinkpad 13 Chromebook)" + select BOARD_GOOGLE_BASEBOARD_GLADOS + select DRIVERS_GENERIC_MAX98357A + select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS + select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS + select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 451b3d4336..476bcf7001 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -19,8 +19,10 @@ #include <baseboard/variant.h> #include <console/console.h> #include <device/device.h> +#include <gpio.h> #include <stdlib.h> #include <soc/nhlt.h> +#include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" @@ -32,6 +34,24 @@ static void mainboard_init(struct device *dev) mainboard_ec_init(); } +static uint8_t adi_codec_enable(void) +{ +#ifdef AUDIO_DB_ID + return gpio_get(AUDIO_DB_ID); +#else + return 1; +#endif +} + +static uint8_t max_codec_enable(void) +{ +#ifdef AUDIO_DB_ID + return gpio_get(AUDIO_DB_ID) ? 0 : 1; +#else + return 1; +#endif +} + static unsigned long mainboard_write_acpi_tables( struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { @@ -58,12 +78,12 @@ static unsigned long mainboard_write_acpi_tables( printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); /* ADI Smart Amps for left and right. */ - if (IS_ENABLED(CONFIG_NHLT_SSM4567)) + if (IS_ENABLED(CONFIG_NHLT_SSM4567) && adi_codec_enable()) if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0)) printk(BIOS_ERR, "Couldn't add ssm4567.\n"); /* MAXIM Smart Amps for left and right. */ - if (IS_ENABLED(CONFIG_NHLT_MAX98357)) { + if (IS_ENABLED(CONFIG_NHLT_MAX98357) && max_codec_enable()) { if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) printk(BIOS_ERR, "Couldn't add max98357.\n"); diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex new file mode 100644 index 0000000000..b5db37cb2e --- /dev/null +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 38 47 54 4D 4C 41 52 2D 4E +55 44 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR-NUD.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR-NUD.spd.hex new file mode 100644 index 0000000000..c9239c3e61 --- /dev/null +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4A 54 4D 4C 41 52 2D 4E +55 44 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex new file mode 100644 index 0000000000..52910465c9 --- /dev/null +++ b/src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 00 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 55 00 00 00 00 00 +20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 +20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/glados/variants/sentry/Makefile.inc b/src/mainboard/google/glados/variants/sentry/Makefile.inc new file mode 100644 index 0000000000..0ebf605ea0 --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/Makefile.inc @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += variant.c +ramstage-y += variant.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0000 Dual Channel 4GB +SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0001 Dual Channel 4GB +SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF # 0b0010 Dual Channel 4GB +SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011 Dual Channel 8GB +SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107-2G-1866 # 0b0100 Dual Channel 8GB +SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0101 Dual Channel 8GB +SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR-NUD # 0b0110 Dual Channel 4GB +SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0111 Dual Channel 8GB +SPD_SOURCES += empty # 0b1000 +SPD_SOURCES += empty # 0b1001 +SPD_SOURCES += empty # 0b1010 +SPD_SOURCES += empty # 0b1011 +SPD_SOURCES += empty # 0b1100 +SPD_SOURCES += empty # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111 + + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/sentry/board_info.txt b/src/mainboard/google/glados/variants/sentry/board_info.txt new file mode 100644 index 0000000000..c4e6be585a --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Sentry (Lenova Thinkpad Chromebook 13) +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/glados/variants/sentry/data.vbt b/src/mainboard/google/glados/variants/sentry/data.vbt Binary files differnew file mode 100644 index 0000000000..0aac82c3b1 --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/data.vbt diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb new file mode 100644 index 0000000000..8af8940e8e --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -0,0 +1,311 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "2" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "4" # 4s + register "PmConfigSlpSusMinAssert" = "3" # 4s + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_RING]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + # Enable Root port 1 and 5. + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkReqNumber[4]" = "2" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) + + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # I2C0 is 3.3V + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Use default SD card detect GPIO configuration + register "sdcard_cd_gpio_default" = "GPP_A7" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + device i2c 39 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_05" + device i2c 15 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 on + chip drivers/i2c/nau8825 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "1" + register "jkdet_pull_up" = "1" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x08" + register "sar_threshold[1]" = "0x12" + register "sar_threshold[2]" = "0x26" + register "sar_threshold[3]" = "0x73" + register "sar_hysteresis" = "0" + register "sar_voltage" = "6" + register "sar_compare_time" = "1" # 1us + register "sar_sampling_time" = "1" # 4us + register "short_key_debounce" = "3" # 30ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "0" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Left Speaker Amp"" + register "uid" = "0" + register "device_present_gpio" = "GPP_E3" + device i2c 34 on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Right Speaker Amp"" + register "uid" = "1" + register "device_present_gpio" = "GPP_E3" + device i2c 35 on end + end + end # I2C #4 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW0_16" + device pci 00.0 on end + end + end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 on end # SDCard + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" + register "device_present_gpio" = "GPP_E3" + register "device_present_gpio_invert" = "1" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..c9913737a2 --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 98 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 77 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 70 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 120 +#define DPTF_TSR0_ACTIVE_AC1 110 +#define DPTF_TSR0_ACTIVE_AC2 47 +#define DPTF_TSR0_ACTIVE_AC3 44 +#define DPTF_TSR0_ACTIVE_AC4 41 +#define DPTF_TSR0_ACTIVE_AC5 38 +#define DPTF_TSR0_ACTIVE_AC6 35 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 70 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 70 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +#undef DPTF_ENABLE_FAN_CONTROL /*Disable DPTF Active policy*/ + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +#ifdef DPTF_ENABLE_FAN_CONTROL +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {100, 0xFFFFFFFF, 4986, 220, 2200}, + Package () {90, 0xFFFFFFFF, 4804, 180, 1800}, + Package () {80, 0xFFFFFFFF, 4512, 145, 1450}, + Package () {70, 0xFFFFFFFF, 4204, 115, 1150}, + Package () {60, 0xFFFFFFFF, 3838, 90, 900}, + Package () {50, 0xFFFFFFFF, 3402, 65, 650}, + Package () {40, 0xFFFFFFFF, 2904, 45, 450}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 81, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 81, 68, 56, 48, 40, + 35, 0, 0, 0 + } +}) +#endif + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 20, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 20, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 20, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 20, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 5000 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 18700, /* PowerLimitMinimum */ + 18700, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/mainboard.asl diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/ec.h b/src/mainboard/google/glados/variants/sentry/include/variant/ec.h new file mode 100644 index 0000000000..f56154bab9 --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/include/variant/ec.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h new file mode 100644 index 0000000000..600a3192c5 --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ +#define GPE_WLAN_WAKE GPE0_DW0_16 + +/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */ +#define GPE_TOUCHPAD_WAKE GPE0_DW0_05 + +/* Input device interrupt configuration */ +#define TOUCHPAD_INT_L GPP_B3_IRQ +#define TOUCHSCREEN_INT_L GPP_E7_IRQ +#define MIC_INT_L GPP_F10_IRQ + +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ +#define EC_SCI_GPI GPE0_DW2_16 +#define EC_SMI_GPI GPP_E15 + +/* + * GPP_E3 is AUDIO_DB_ID. + * It is a dual purpose GPIO, used for Audio Daughter + * Board Identification & to control the shutdown mode pin + * of the Maxim amp. + */ +#define AUDIO_DB_ID GPP_E3 + +/* SD controller needs additional card detect GPIO to support RTD3 */ +#define GPIO_SD_CARD_DETECT GPP_A7 + +#ifndef __ACPI__ +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), +/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), +/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), +/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), +/* GYRO_INT */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), +/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), +/* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), +/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), +/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), +/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), +/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), +/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), +/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), +/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), +/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), +/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), +/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), +/* USB_CTL */ PAD_CFG_NC(GPP_C7), +/* UART0_RXD */ PAD_CFG_NC(GPP_C8), +/* UART0_TXD */ PAD_CFG_NC(GPP_C9), +/* NFC_RST* */ PAD_CFG_NC(GPP_C10), +/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP), +/* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), +/* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), +/* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), +/* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), +/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), +/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), +/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), +/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), +/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), +/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), +/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), +/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), +/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), +/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), +/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), +/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), +/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), +/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), +/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), +/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), +/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), +/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), +/* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), +/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), +/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), +/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), +/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), +/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PU, DEEP, NF1), +/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* GPD7 */ PAD_CFG_NC(GPD7), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), +/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), +/* LANPHYC */ PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ +}; + +#endif + +#endif diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c new file mode 100644 index 0000000000..00f49fecf7 --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <baseboard/variant.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +#define K4E6E304EE_MEM_ID 0x3 + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 6, 5, 4, 7 }, + { 2, 3, 0, 1, 6, 7, 4, 5 } }; + + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; + + /* Strengthen the Rcomp Target Ctrl for K4E6E304EE_MEM_ID */ + const u16 StrengthendRcompTarget[5] = { 100, 40, 40, 21, 40 }; + + /* Default Rcomp Target assignment */ + const u16 *targeted_rcomp = RcompTarget; + + memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); + memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); + memcpy(pei_data->RcompResistor, RcompResistor, + sizeof(RcompResistor)); + + /* Override Rcomp Target assignment for specific SKU(s) */ + if (pei_data->mem_cfg_id == K4E6E304EE_MEM_ID) + targeted_rcomp = StrengthendRcompTarget; + + memcpy(pei_data->RcompTarget, targeted_rcomp, + sizeof(pei_data->RcompTarget)); +} |