diff options
| author | Matt DeVillier <matt.devillier@puri.sm> | 2020-09-23 17:15:34 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-28 09:33:54 +0000 |
| commit | 25a2ca96283dd12b85361025cd8a092da254640c (patch) | |
| tree | 208c6d2d854625a7f5c2377835f0aae6e9635e3e /src | |
| parent | b5eae2868bf699043b41b31068841ed1015d424c (diff) | |
mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params
Some Librem Minis exhibit issues with 6Gbps SATA operation on certain
SSDs, setting the Receiver Equalization Boost Magnitude adjustment
resolves this, so limiting SATA speeds to 3Gbps is no longer needed.
Test: build/boot Librem Mini with Crucial SATA SSD, observe no issues
booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7
Change-Id: I8b3cbcff7f181bcab35d71e859033578c822bb20
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/purism/librem_whl/ramstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/romstage.c | 9 |
2 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_whl/ramstage.c index 07ede66505..56ed1b7844 100644 --- a/src/mainboard/purism/librem_whl/ramstage.c +++ b/src/mainboard/purism/librem_whl/ramstage.c @@ -10,7 +10,4 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) size_t num_gpios; const struct pad_config *gpio_table = variant_gpio_table(&num_gpios); cnl_configure_pads(gpio_table, num_gpios); - - /* Limit SATA speed to 3Gbps until correct HSIO PHY settings determined */ - params->SataSpeedLimit = 2; } diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_whl/romstage.c index 9f8d600950..3a3ca6b491 100644 --- a/src/mainboard/purism/librem_whl/romstage.c +++ b/src/mainboard/purism/librem_whl/romstage.c @@ -48,5 +48,12 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { - cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + cannonlake_memcfg_init(mem_cfg, &memcfg); + + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 2; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; } |