vc/amd/pi/0067F00: add option to add AGESA binary PI as stage

Stage addition to CBFS allows relocation to happen on the fly. Take
advantage of that by adding AGESA binary PI as a stage file so that
each instance will be relocated properly within CBFS. Without this
patch Chrome OS having multiple CBFS instances just redirects the
AGESA calls back into RO which is inappropriate.

BUG=b:65442265,b:68141063
TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and
     noted each instance in Chrome OS build was relocated.

Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

3 files changed, 70 insertions, 6 deletions

diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c
index b1f03cb178..cc572075af 100644
--- a/src/soc/amd/common/block/pi/agesawrapper.c
+++ b/src/soc/amd/common/block/pi/agesawrapper.c
@@ -381,22 +381,68 @@ AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus)
 	return Status;
 }
 
+static int agesa_locate_file(const char *name, struct region_device *rdev,
+				uint32_t type)
+{
+	struct cbfsf fh;
+
+	if (cbfs_boot_locate(&fh, name, &type))
+		return -1;
+
+	cbfs_file_data(rdev, &fh);
+	return 0;
+}
+
+static int agesa_locate_raw_file(const char *name, struct region_device *rdev)
+{
+	return agesa_locate_file(name, rdev, CBFS_TYPE_RAW);
+}
+
+static int agesa_locate_stage_file(const char *name, struct region_device *rdev)
+{
+	const size_t metadata_sz = sizeof(struct cbfs_stage);
+
+	if (agesa_locate_file(name, rdev, CBFS_TYPE_STAGE))
+		return -1;
+
+	/* Peel off the cbfs stage metadata. */
+	return rdev_chain(rdev, rdev, metadata_sz,
+			region_device_sz(rdev) - metadata_sz);
+}
+
 const void *agesawrapper_locate_module (const CHAR8 name[8])
 {
 	const void* agesa;
 	const AMD_IMAGE_HEADER* image;
-	const AMD_MODULE_HEADER* module;
+	struct region_device rdev;
 	size_t file_size;
+	const char *fname = CONFIG_AGESA_CBFS_NAME;
+	int ret;
+
+	if (IS_ENABLED(CONFIG_AGESA_BINARY_PI_AS_STAGE))
+		ret = agesa_locate_stage_file(fname, &rdev);
+	else
+		ret = agesa_locate_raw_file(fname, &rdev);
+
+	if (ret)
+		return NULL;
 
-	agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME,
-						CBFS_TYPE_RAW, &file_size);
+	file_size = region_device_sz(&rdev);
+
+	/* Assume boot device is memory mapped so the mapping can leak. */
+	assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
+
+	agesa = rdev_mmap_full(&rdev);
 
 	if (!agesa)
 		return NULL;
-	image =  LibAmdLocateImage(agesa, agesa + file_size - 1, 4096, name);
-	module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset;
 
-	return module;
+	image =  LibAmdLocateImage(agesa, agesa + file_size, 4096, name);
+
+	if (!image)
+		return NULL;
+
+	return (AMD_MODULE_HEADER *)image->ModuleInfoOffset;
 }
 
 static MODULE_ENTRY agesa_dispatcher CAR_GLOBAL;
diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc
index a5e644e78c..f1e340e751 100644
--- a/src/vendorcode/amd/pi/00670F00/Makefile.inc
+++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc
@@ -125,7 +125,15 @@ ramstage-libs += $(agesa_output_path)/libagesa.a
 
 cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME)
 $(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE)
+ifeq ($(CONFIG_AGESA_BINARY_PI_AS_STAGE),y)
+$(CONFIG_AGESA_CBFS_NAME)-type := stage
+$(CONFIG_AGESA_CBFS_NAME)-options :=  --xip
+# 4KiB alignment to handle any interior alignment. Current AGESA only has
+# 64 byte alignment.
+$(CONFIG_AGESA_CBFS_NAME)-align := 4096
+else
 $(CONFIG_AGESA_CBFS_NAME)-type := raw
 $(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION)
+endif
 
 endif
diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig
index 3743d07580..8c38a790ea 100644
--- a/src/vendorcode/amd/pi/Kconfig
+++ b/src/vendorcode/amd/pi/Kconfig
@@ -49,6 +49,15 @@ config AGESA_BINARY_PI_FILE
 	help
 	  Specify the binary file to use for AMD platform initialization.
 
+config AGESA_BINARY_PI_AS_STAGE
+	bool "AGESA Binary PI is added as stage to CBFS."
+	depends on SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_STONEYRIDGE_FP4
+	help
+	  AGESA will be added as a stage utilizing --xip cbfstool options
+	  as needed relocating the image to the proper location in memory-mapped
+	  cpu address space. It's required that the file be in ELF format
+	  containing the relocations necessary for relocating at runtime.
+
 config AGESA_CBFS_NAME
 	string
 	default "AGESA"
@@ -56,6 +65,7 @@ config AGESA_CBFS_NAME
 config AGESA_BINARY_PI_LOCATION
 	hex "AGESA PI binary address in ROM"
 	default 0xFFE00000
+	depends on !AGESA_BINARY_PI_AS_STAGE
 	help
 	  Specify the ROM address at which to store the binary Platform
 	  Initialization code.