soc/intel/skylake: Enable SMBus depending on devicetree configuration

Currently SMBus gets enabled by the option SmbusEnable, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SMBus controller.

I checked all corresponding mainboards if the devicetree configuration
matches the SmbusEnable setting.

Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner

24 files changed, 4 insertions, 27 deletions

diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 69469b911b..377de0b951 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -51,7 +51,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "0"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 9b56f429a9..0b3b768d4f 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -28,7 +28,6 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# FSP Configuration
-	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "ScsSdCardEnabled" = "0"
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 4b08819628..5911624b5c 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -37,7 +37,6 @@ chip soc/intel/skylake
 
 	# FSP Configuration
 	register "EnableAzalia" = "1"
-	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
index 1af83259be..dfdcf5a4f3 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
@@ -32,7 +32,6 @@ chip soc/intel/tigerlake
 	register "SataEnable" = "1"
 	register "SataMode" = "0"
 	register "SataSalpSupport" = "1"
-	register "SmbusEnable" = "1"
 
 	# TODO: the lengths are all MID for right now.
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C Port 1
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 767c77b907..14d8cc40c3 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -44,7 +44,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 250b96d8ff..0ce9002d7d 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -75,7 +75,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index bbfa79f1b5..856d749009 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -46,7 +46,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 7c4928d47e..4af8c42958 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -50,7 +50,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "1"
 	register "SaImguEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 7bbddbdf3a..bed537bdb6 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -40,7 +40,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "1"
 	register "SaImguEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index e9514e0bca..e9f8b1d8a5 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
 	register "SaImguEnable" = "0"
 	register "ScsEmmcEnabled" = "1"
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index e9d7dea3c2..de14503a88 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -40,7 +40,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "1"
 	register "SaImguEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index a5c905eed9..24ee14c3d1 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -45,7 +45,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "1"
 	register "SaImguEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 32429f9ced..3b9c76168f 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -50,7 +50,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
 	register "SaImguEnable" = "0"
 	register "ScsEmmcEnabled" = "1"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 2970a2e430..eb3cff351c 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -40,7 +40,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "1"
 	register "SaImguEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
index b7e1cc0ce1..839245961c 100644
--- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
@@ -23,7 +23,6 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# FSP Configuration
-	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "ScsSdCardEnabled" = "2"
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 51ff562153..9e6993c95b 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -27,7 +27,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "ScsSdCardEnabled" = "2"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 5a24705206..40d2603675 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -21,7 +21,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "ScsSdCardEnabled" = "0"
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index 67b56ff830..08d80d5750 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -52,7 +52,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "0"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index ef2cfbb9a6..d1f0d4b205 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -41,7 +41,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "0"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 6943505e40..b9d385b8e3 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -57,7 +57,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "0"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index 8a369b79b9..7e96fe269e 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -37,7 +37,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "0"
 	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index cf0d6bcb7f..89e5e1a180 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -7,7 +7,6 @@ chip soc/intel/skylake
 	register "speed_shift_enable" = "1"
 
 	# FSP Configuration
-	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
 	register "ScsSdCardEnabled" = "0"
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b243bdea75..243e6ee851 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -272,9 +272,6 @@ struct soc_intel_skylake_config {
 	struct usb3_port_config usb3_ports[10];
 	u8 SsicPortEnable;
 
-	/* SMBus */
-	u8 SmbusEnable;
-
 	/*
 	 * SerialIO device mode selection:
 	 *
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 99f444ad5e..8e789bce80 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -272,6 +272,7 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
 	const struct soc_intel_skylake_config *config;
+	const struct device *dev;
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 	FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
 
@@ -296,8 +297,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
 	m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
 
-	/* Enable SMBus controller based on config */
-	m_cfg->SmbusEnable = config->SmbusEnable;
+	/* Enable SMBus controller */
+	dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
+	m_cfg->SmbusEnable = dev ? dev->enabled : 0;
 
 	/* Set primary graphic device */
 	soc_primary_gfx_config_params(m_cfg, config);