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authorSridhar Siricilla <sridhar.siricilla@intel.com>2021-04-08 13:27:13 +0530
committerPatrick Georgi <pgeorgi@google.com>2021-04-10 20:23:07 +0000
commitfce0954f456d05f2cb7200eb9508710c1801c9f6 (patch)
tree3c74b8a6014c6e5da802d0cf8fd6a4956e549e66 /src
parentf62bbc8388dd7ce6c34b40bc9a0bd21ab32ab96c (diff)
mb/intel/shadowmountain: Enable Bluetooth config in the devicetree
The patch enables Bluetooth config in the devicetree and removes non-existent Bluetooth PCI interface. TEST=Verified by checking Garfield Peak controller's PID:VID(8087:0033) in the lsusb ouput. Output of lsusb: Bus 004 Device 003: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN Bus 004 Device 002: ID 0bda:0411 Realtek Semiconductor Corp. 4-Port USB 3.0 Hub Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub Bus 003 Device 003: ID 0781:55a9 SanDisk Corp. Dual Drive Bus 003 Device 004: ID 413c:2113 Dell Computer Corp. Dell KB216 Wired Keyboard Bus 003 Device 002: ID 0bda:5411 Realtek Semiconductor Corp. 4-Port USB 2.0 Hub Bus 003 Device 005: ID 8087:0033 Intel Corp. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I7a54d344ef1b0418bee56e7308977a61604b954a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52182 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 8b3178408d..5b3dbbf583 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -20,6 +20,10 @@ chip soc/intel/alderlake
# Enable heci communication
register "HeciEnabled" = "1"
+ # Enable CNVi Bluetooth
+ register "CnviBtCore" = "true"
+
+
# FSP configuration
register "SaGv" = "SaGv_Disabled"
@@ -208,7 +212,6 @@ chip soc/intel/alderlake
device pci 0e.0 off end # VMD
device pci 10.0 off end
device pci 10.1 off end
- device pci 10.2 on end # CNVi: BT
device pci 10.6 off end # THC0
device pci 10.7 off end # THC1
device pci 11.0 off end