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authorKarthikeyan Ramasubramanian <kramasub@google.com>2024-07-29 13:37:36 -0600
committerJon Murphy <jpmurphy@google.com>2024-07-31 14:11:30 +0000
commitfa66d33336fcf4358c1bacd84ae9427f8dfb59ba (patch)
treede01edf8b12b6558516fd02e833ebb844d91da25 /src
parent8200a9ac387ca35d93b307ff01038d686c9281e4 (diff)
soc/intel/adl: Update DCACHE_BSP_STACK_SIZE
During the stages which use Cache-as-RAM (CAR), coreboot needs more than 1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly. BUG=None TEST=Build Brox BIOS image and boot to OS. Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83680 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/alderlake/Kconfig4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 470dbf4d8e..632798e6a1 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -191,12 +191,12 @@ config DCACHE_RAM_SIZE
config DCACHE_BSP_STACK_SIZE
hex
- default 0x80400
+ default 0x88000
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be
sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
- (~1KiB).
+ (~32KiB).
config FSP_TEMP_RAM_SIZE
hex