diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-21 11:26:48 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-25 10:32:07 +0100 |
| commit | f6fe2f1286f2551ae8d9732f949a51eb6c975363 (patch) | |
| tree | ff76d14402e2eb195e34873fdce1b9296f5fb7af /src | |
| parent | 619a245def2ac424beeb8a68d246a78849acd0cc (diff) | |
AGESA binaryPI: Fix cache-as-ram for x86_64
AMD_ENABLE_STACK was not called on x86_64 path for AGESA, while
it was for binaryPI.
Comments on BIST and cpu_init_detected were reversed, so fix those
too.
Change-Id: I0ddfaf51feb386a56d488c29d60171b05ff6fbc4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17551
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/amd/agesa/cache_as_ram.inc | 7 | ||||
| -rw-r--r-- | src/cpu/amd/pi/cache_as_ram.inc | 6 |
2 files changed, 8 insertions, 5 deletions
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 293e9a5077..24db6001ea 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -61,6 +61,8 @@ cache_as_ram_setup: post_code(0xa1) + AMD_ENABLE_STACK + #ifdef __x86_64__ /* switch to 64 bit long mode */ mov %esi, %ecx @@ -103,10 +105,10 @@ cache_as_ram_setup: # use call far to switch to 64-bit code segment ljmp $0x18, $1f 1: - /* Pass the BIST result */ + /* Pass the cpu_init_detected */ cvtsd2si %xmm1, %esi - /* Pass the cpu_init_detected */ + /* Pass the BIST result */ cvtsd2si %xmm0, %edi /* align the stack */ @@ -117,7 +119,6 @@ cache_as_ram_setup: .code32 #else - AMD_ENABLE_STACK /* Restore the BIST result */ cvtsd2si %xmm0, %edx diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc index 40ec1b2fc2..24db6001ea 100644 --- a/src/cpu/amd/pi/cache_as_ram.inc +++ b/src/cpu/amd/pi/cache_as_ram.inc @@ -62,6 +62,7 @@ cache_as_ram_setup: post_code(0xa1) AMD_ENABLE_STACK + #ifdef __x86_64__ /* switch to 64 bit long mode */ mov %esi, %ecx @@ -104,10 +105,10 @@ cache_as_ram_setup: # use call far to switch to 64-bit code segment ljmp $0x18, $1f 1: - /* Pass the BIST result */ + /* Pass the cpu_init_detected */ cvtsd2si %xmm1, %esi - /* Pass the cpu_init_detected */ + /* Pass the BIST result */ cvtsd2si %xmm0, %edi /* align the stack */ @@ -118,6 +119,7 @@ cache_as_ram_setup: .code32 #else + /* Restore the BIST result */ cvtsd2si %xmm0, %edx |