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authorStefan Reinauer <stepan@coresystems.de>2010-01-17 13:54:08 +0000
committerStefan Reinauer <stepan@openbios.org>2010-01-17 13:54:08 +0000
commitf6eb88adfb8535cdd6c71d5adeed6ca8ed78952d (patch)
tree1ae0414404187a0713de2dadf9fbc4cb69575496 /src
parent2e73e1975149aea1ac78dced3d9e8b0b7f684113 (diff)
Initial PCIe tuning: Enable Active State Power Management (ASPM)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/devices/pciexp_device.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/src/devices/pciexp_device.c b/src/devices/pciexp_device.c
index 461c3b6c7a..ea9c791272 100644
--- a/src/devices/pciexp_device.c
+++ b/src/devices/pciexp_device.c
@@ -34,8 +34,16 @@ static void pciexp_tune_dev(device_t dev)
/* error... */
return;
}
- // printk_debug("PCIe: tuning %s\n", dev_path(dev));
- /* TODO: Implement PCI Express tuning. */
+#ifdef CONFIG_PCIE_TUNING
+ printk_debug("PCIe: tuning %s\n", dev_path(dev));
+
+ // TODO make this depending on ASPM
+ /* Enable ASPM Role Based Error Reporting */
+ u32 reg32;
+ reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
+ reg32 |= PCI_EXP_DEVCAP_RBER;
+ pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+#endif
}
unsigned int pciexp_scan_bus(struct bus *bus,