soc/intel/common: Add CPU and PCIe IDs for Snow Ridge platform

CPU and PCIe IDs are from Intel Atom Processor C5100, C5300,
P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0.

Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83314
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 22 insertions, 0 deletions

diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index ae58110e0e..ad66025d5f 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -83,5 +83,12 @@
 #define CPUID_LUNARLAKE_A0_1		0xb06d0
 #define CPUID_LUNARLAKE_A0_2		0xb06d1
 #define CPUID_PANTHERLAKE_A0		0xc06c0
+#define CPUID_SNOWRIDGE_A0		0x80660
+#define CPUID_SNOWRIDGE_A1		0x80661
+#define CPUID_SNOWRIDGE_A2		0x80662
+#define CPUID_SNOWRIDGE_A3		0x80663
+#define CPUID_SNOWRIDGE_B0		0x80664
+#define CPUID_SNOWRIDGE_B1		0x80665
+#define CPUID_SNOWRIDGE_C0		0x80667
 
 #endif /* CPU_INTEL_CPU_IDS_H */
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 8b2de41b8b..b721bb4df6 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3232,6 +3232,7 @@
 #define PCI_DID_INTEL_PTL_U_H_ESPI_29			0xe31d
 #define PCI_DID_INTEL_PTL_U_H_ESPI_30			0xe31e
 #define PCI_DID_INTEL_PTL_U_H_ESPI_31			0xe31f
+#define PCI_DID_INTEL_SNR_LPC					0x18dc
 
 /* Intel PCIE device ids  */
 #define PCI_DID_INTEL_LPT_H_PCIE_RP1			0x8c10
@@ -4425,6 +4426,7 @@
 #define PCI_DID_INTEL_PTL_U_ID_1		0xb000
 #define PCI_DID_INTEL_PTL_H_ID_1		0xb001
 #define PCI_DID_INTEL_PTL_H_ID_2		0xb002
+#define PCI_DID_INTEL_SNR_ID			0x09a2
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22
@@ -4502,6 +4504,7 @@
 #define PCI_DID_INTEL_PTL_H_TCSS_XHCI		0xe431
 #define PCI_DID_INTEL_PTL_U_H_XHCI		0xe37d
 #define PCI_DID_INTEL_PTL_U_H_TCSS_XHCI		0xe331
+#define PCI_DID_INTEL_SNR_XHCI			0x18d0
 
 /* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
@@ -4534,6 +4537,7 @@
 #define PCI_DID_INTEL_PTL_H_P2SB2		0xe44c
 #define PCI_DID_INTEL_PTL_U_H_P2SB		0xe320
 #define PCI_DID_INTEL_PTL_U_H_P2SB2		0xe34c
+#define PCI_DID_INTEL_SNR_P2SB			0x18dd
 
 /* Intel SRAM device Ids */
 #define PCI_DID_INTEL_APL_SRAM			0x5aec
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index d5cc883973..95e52d5d9c 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -95,6 +95,13 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_B0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_C0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_H0, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_SNOWRIDGE_A0, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_SNOWRIDGE_A1, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_SNOWRIDGE_A2, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_SNOWRIDGE_A3, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_SNOWRIDGE_B0, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_SNOWRIDGE_B1, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_SNOWRIDGE_C0, CPUID_EXACT_MATCH_MASK },
 	CPU_TABLE_END
 };
 
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index 147c4f1621..ef14914968 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -447,6 +447,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ADP_M_N_ESPI_30,
 	PCI_DID_INTEL_ADP_M_N_ESPI_31,
 	PCI_DID_INTEL_SPR_ESPI_1,
+	PCI_DID_INTEL_SNR_LPC,
 	0
 };
 
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index 16f78da6c7..27e969cb55 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -159,6 +159,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ADP_M_P2SB,
 	PCI_DID_INTEL_SPR_SP_P2SB,
 	PCI_DID_INTEL_RPP_S_P2SB,
+	PCI_DID_INTEL_SNR_P2SB,
 	0,
 };
 
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 48dbbf1508..5d9ac15fbc 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -541,6 +541,7 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_RPL_P_ID_6,
 	PCI_DID_INTEL_RPL_P_ID_7,
 	PCI_DID_INTEL_RPL_P_ID_8,
+	PCI_DID_INTEL_SNR_ID,
 	0
 };
 
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index c1f300a2a4..6d35f39afb 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -152,6 +152,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ADP_S_XHCI,
 	PCI_DID_INTEL_ADP_M_XHCI,
 	PCI_DID_INTEL_RPP_S_XHCI,
+	PCI_DID_INTEL_SNR_XHCI,
 	0
 };