diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-05-17 12:25:40 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-18 10:11:45 +0000 |
| commit | f6004114ec3807e15acbc01cee45d4f83254bae2 (patch) | |
| tree | 671259b138aac9df80806a83f9f8468ba21e8631 /src | |
| parent | 71e797478447e43b9d3be0cae13948a0ea9f0082 (diff) | |
intelblocks/gpio: Add NAVFWE bit to PAD_CFG_DW0 mask definition
Definition for NAV_FWE BIT was added in commit e6e8b3d
Even if try to set this BIT it was not getting set since PAD_CFG_DW0
mask will make it 0 since this bit was not part of mask.
Adding NAV_FWE to mask will resolve this issue and BIT will be set/unset
as per programming in mainboard.
TEST=Check GPIO register dump and see if BIT is getting set properly.
Change-Id: I970ae81ed36da45c3acc61814980b2e6ff889445
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54350
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/gpio/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 8dc92ffb34..8f1c3a5601 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -24,7 +24,7 @@ PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |\ PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK | \ PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL | \ - PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | \ + PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | PAD_CFG0_NAFVWE_ENABLE |\ PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) |