diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2018-05-15 00:01:44 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-05-22 15:52:11 +0000 |
| commit | ee3158fd6cf27397384550de613085cc11426009 (patch) | |
| tree | 0be98d813855a24b43cf32cac9de5e6851412722 /src | |
| parent | 2626ecdf5050d02f580a886b03bdaeb892dc4f11 (diff) | |
vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.3
Update FSP header files to match FSP Reference Code Release v2.0.3 for
Gemimilake
CQ-DEPEND=CL:*627827
Change-Id: I17438f18fc3a1ea7ad9bd69a06adb1330d917257
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/26285
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h | 2 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h | 22 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h | 19 |
3 files changed, 34 insertions, 9 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h index 354dd8a91a..20bd9afe1b 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h index 1898c09976..c25fd406e5 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h @@ -998,9 +998,23 @@ typedef struct { **/ UINT32 CpuPeiApWakeupBufferAddr; -/** Offset 0x0180 +/** Offset 0x0180 - SkipPciePowerSequence + UPD To Skip PciePowerSequence, 0: Initialize(Default), 1: Skip **/ - UINT8 ReservedFspmUpd[4]; + UINT8 SkipPciePowerSequence; + +/** Offset 0x0181 +**/ + UINT8 RevAligmentFspmUpd[7]; + +/** Offset 0x0188 - SkipMemoryTestUpd + UPD To Skip CpuMemoryTest, 0: Initialize(Default), 1: Skip +**/ + UINT8 SkipMemoryTestUpd; + +/** Offset 0x0189 +**/ + UINT8 ReservedFspmUpd[7]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -1019,9 +1033,9 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0184 +/** Offset 0x0190 **/ - UINT8 UnusedUpdSpace1[130]; + UINT8 UnusedUpdSpace1[118]; /** Offset 0x0206 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h index 970f0e2d89..1cbcb69991 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h @@ -1708,9 +1708,16 @@ typedef struct { **/ UINT8 UsbPdoProgramming; -/** Offset 0x03AA +/** Offset 0x03AA - Skip LPSS SPI Private Clock Parameter Programming + When this is skipped, boot loader must program LPSS SPI PCP. 0: Initialize(Default), + <b>1: Skip + $EN_DIS +**/ + UINT8 SkipSpiPCP; + +/** Offset 0x03AB **/ - UINT8 ReservedFspsUpd[6]; + UINT8 ReservedFspsUpd[5]; } FSP_S_CONFIG; /** Fsp S SGX Configuration @@ -1764,7 +1771,7 @@ typedef struct { /** Offset 0x03F8 **/ - UINT8 ReservedFspsSgxUpd[6]; + UINT8 ReservedFspsSgxUpd[8]; } FSP_S_SGX_CONFIG; /** Fsp S UPD Configuration @@ -1787,7 +1794,11 @@ typedef struct { **/ FSP_S_SGX_CONFIG FspsSgxConfig; -/** Offset 0x03FE +/** Offset 0x0400 +**/ + UINT8 UnusedUpdSpace9[6]; + +/** Offset 0x0406 **/ UINT16 UpdTerminator; } FSPS_UPD; |