mb/emulation/qemu-riscv: Change to -bios option

This changes the virt target so that it can be run with the -bios option
and a pflash backend for the flash. QEMU can now be run as follows:

qemu -M virt -m 1G -nographic -bios build/coreboot.rom \
        -drive if=pflash,file=./build/coreboot.rom,format=raw

coreboot will start in DRAM, but still have a flash to put CBFS onto and
to load subsequent stages and payload from.

Tested bootflow:
coreboot -> OpenSBI -> Linux -> u-root

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>

11 files changed, 88 insertions, 50 deletions

diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig
index f00b1fbdce..5f596b87c0 100644
--- a/src/mainboard/emulation/Kconfig
+++ b/src/mainboard/emulation/Kconfig
@@ -1,5 +1,9 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+# ugly to put it in here, but unavoidable
+config SEPARATE_ROMSTAGE
+	default n if BOARD_EMULATION_QEMU_RISCV
+
 if VENDOR_EMULATION
 
 choice
diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig
index af4416d0c1..94f9e56c5a 100644
--- a/src/mainboard/emulation/qemu-riscv/Kconfig
+++ b/src/mainboard/emulation/qemu-riscv/Kconfig
@@ -1,8 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 # To execute, do:
-# qemu-system-riscv64 -M virt -m 1024M -nographic -bios build/coreboot.rom
-
+# qemu-system-riscv64 -M virt -m 1024M -nographic -bios build/coreboot.rom \
+#                     -drive if=pflash,file=build/coreboot.rom,format=raw
 
 if BOARD_EMULATION_QEMU_RISCV_RV64
 
@@ -22,12 +22,18 @@ if BOARD_EMULATION_QEMU_RISCV
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select SOC_UCB_RISCV
-	select BOARD_ROMSIZE_KB_16384
-	select BOOT_DEVICE_NOT_SPI_FLASH
+	select BOARD_ROMSIZE_KB_32768
 	select MISSING_BOARD_RESET
 	select DRIVERS_UART_8250MEM
 	select RISCV_HAS_OPENSBI
+	select ARCH_RISCV_S
+	select ARCH_RISCV_U
+	select ARCH_RISCV_PMP
+	select ARCH_BOOTBLOCK_RISCV
+	select ARCH_VERSTAGE_RISCV
+	select ARCH_ROMSTAGE_RISCV
+	select ARCH_RAMSTAGE_RISCV
+	select RISCV_USE_ARCH_TIMER
 
 config MEMLAYOUT_LD_FILE
 	string
@@ -43,6 +49,25 @@ config MAX_CPUS
 	int
 	default 1
 
+config RISCV_ARCH
+	string
+	default "rv64imafd" if ARCH_RISCV_RV64
+	default "rv32im" if ARCH_RISCV_RV32
+
+config RISCV_ABI
+	string
+	default "lp64d" if ARCH_RISCV_RV64
+	default "ilp32" if ARCH_RISCV_RV32
+
+config RISCV_CODEMODEL
+	string
+	default "medany" if ARCH_RISCV_RV64
+	default "medany" if ARCH_RISCV_RV32
+
+config RISCV_WORKING_HARTID
+	int
+	default 0
+
 config DRAM_SIZE_MB
 	int
 	default 16383
@@ -54,20 +79,8 @@ config OPENSBI_PLATFORM
 	string
 	default "generic"
 
-# ugly, but CBFS is placed in DRAM...
 config OPENSBI_TEXT_START
 	hex
-	default 0x80040000 if COREBOOT_ROMSIZE_KB_256
-	default 0x80080000 if COREBOOT_ROMSIZE_KB_512
-	default 0x80100000 if COREBOOT_ROMSIZE_KB_1024
-	default 0x80200000 if COREBOOT_ROMSIZE_KB_2048
-	default 0x80400000 if COREBOOT_ROMSIZE_KB_4096
-	default 0x80600000 if COREBOOT_ROMSIZE_KB_6144
-	default 0x80800000 if COREBOOT_ROMSIZE_KB_8192
-	default 0x80a00000 if COREBOOT_ROMSIZE_KB_10240
-	default 0x80c00000 if COREBOOT_ROMSIZE_KB_12288
-	default 0x81000000 if COREBOOT_ROMSIZE_KB_16384
-	default 0x82000000 if COREBOOT_ROMSIZE_KB_32768
-	default 0x84000000 if COREBOOT_ROMSIZE_KB_65536
+	default 0x80020000
 
 endif #  BOARD_EMULATION_QEMU_RISCV
diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.mk b/src/mainboard/emulation/qemu-riscv/Makefile.mk
index 1a8342d2ca..bed0f80392 100644
--- a/src/mainboard/emulation/qemu-riscv/Makefile.mk
+++ b/src/mainboard/emulation/qemu-riscv/Makefile.mk
@@ -1,16 +1,21 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+bootblock-y += mainboard.c
 bootblock-y += uart.c
 bootblock-y += rom_media.c
 bootblock-y += clint.c
 
+romstage-y += cbmem.c
 romstage-y += romstage.c
 romstage-y += uart.c
 romstage-y += rom_media.c
 romstage-y += clint.c
 
+ramstage-y += mainboard.c
 ramstage-y += uart.c
 ramstage-y += rom_media.c
 ramstage-y += clint.c
+ramstage-y += cbmem.c
+ramstage-y += chip.c
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/emulation/qemu-riscv/cbmem.c b/src/mainboard/emulation/qemu-riscv/cbmem.c
new file mode 100644
index 0000000000..10ca2cd87f
--- /dev/null
+++ b/src/mainboard/emulation/qemu-riscv/cbmem.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbmem.h>
+#include <symbols.h>
+#include <ramdetect.h>
+#include <console/console.h>
+
+uintptr_t cbmem_top_chipset(void)
+{
+	//TODO get memory range from QEMUs FDT
+	size_t dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB);
+	return (uintptr_t)_dram + dram_mb_detected * MiB;
+}
diff --git a/src/mainboard/emulation/qemu-riscv/chip.c b/src/mainboard/emulation/qemu-riscv/chip.c
new file mode 100644
index 0000000000..5cec284de5
--- /dev/null
+++ b/src/mainboard/emulation/qemu-riscv/chip.c
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_emulation_qemu_riscv_ops = {
+	.name = "QEMU RISC-V",
+};
diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb
index 120af99156..9de1b75f50 100644
--- a/src/mainboard/emulation/qemu-riscv/devicetree.cb
+++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb
@@ -1,5 +1,5 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-chip soc/ucb/riscv
+chip mainboard/emulation/qemu-riscv
 	device cpu_cluster 0 on end
 end
diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
index 27baeb7720..542e39592b 100644
--- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
+++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
@@ -4,4 +4,5 @@
 #define QEMU_VIRT_PLIC		0x0c000000
 #define QEMU_VIRT_UART0		0x10000000
 #define QEMU_VIRT_VIRTIO	0x10001000
+#define QEMU_VIRT_FLASH		0x20000000
 #define QEMU_VIRT_DRAM		0x80000000
diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c
index f0f0740484..e17ce13d43 100644
--- a/src/mainboard/emulation/qemu-riscv/mainboard.c
+++ b/src/mainboard/emulation/qemu-riscv/mainboard.c
@@ -3,18 +3,15 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <symbols.h>
-#include <ramdetect.h>
+#include <cbmem.h>
 
 static void mainboard_enable(struct device *dev)
 {
-	size_t dram_mb_detected;
-
 	if (!dev) {
 		die("No dev0; die\n");
 	}
 
-	dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB);
-	ram_range(dev, 0, (uintptr_t)_dram, dram_mb_detected * MiB);
+	ram_from_to(dev, 0, (uintptr_t)_dram, (uintptr_t)cbmem_top());
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld
index 4fdeb9dccb..9c16496e11 100644
--- a/src/mainboard/emulation/qemu-riscv/memlayout.ld
+++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld
@@ -4,28 +4,17 @@
 #include <arch/header.ld>
 #include <mainboard/addressmap.h>
 
-// Stages start after CBFS in DRAM
-#define STAGES_START (QEMU_VIRT_DRAM + CONFIG_ROM_SIZE)
-
 SECTIONS
 {
-	// the virt target doesn't emulate flash and just puts the CBFS into DRAM.
-	// fake SRAM where CBFS resides. It's only done for better integration.
-	SRAM_START(QEMU_VIRT_DRAM)
-	BOOTBLOCK(QEMU_VIRT_DRAM, 64K)
-	// CBFS goes here
-	SRAM_END(STAGES_START)
-	DRAM_START(STAGES_START)
+	REGION(flash, QEMU_VIRT_FLASH, CONFIG_ROM_SIZE, 0) \
 
-#if ENV_SEPARATE_ROMSTAGE
-	ROMSTAGE(STAGES_START, 128K)
-#endif
-#if ENV_RAMSTAGE
-	REGION(opensbi, STAGES_START, 128K, 4K)
-#endif
-	PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K)
-	FMAP_CACHE(STAGES_START + 136K, 2K)
-	CBFS_MCACHE(STAGES_START + 138K, 8K)
-	RAMSTAGE(STAGES_START + 200K, 16M)
-	STACK(STAGES_START + 200K + 16M, 4K)
+	DRAM_START(QEMU_VIRT_DRAM)
+	BOOTBLOCK(QEMU_VIRT_DRAM, 128K)
+	OPENSBI(QEMU_VIRT_DRAM + 128K, 256K)
+	ROMSTAGE(QEMU_VIRT_DRAM + 128K + 256K, 256K)
+	RAMSTAGE(QEMU_VIRT_DRAM + 128K + 256K + 256K, 2M)
+	PRERAM_CBMEM_CONSOLE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M,  8K)
+	FMAP_CACHE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K,  2K)
+	CBFS_MCACHE(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K,  10K)
+	STACK(QEMU_VIRT_DRAM + 128K + 256K + 256K + 2M + 8K + 2K + 10K, 4M)
 }
diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c
index 15989f2aea..3c636ced0d 100644
--- a/src/mainboard/emulation/qemu-riscv/rom_media.c
+++ b/src/mainboard/emulation/qemu-riscv/rom_media.c
@@ -1,11 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 #include <boot_device.h>
 #include <symbols.h>
+#include <mainboard/addressmap.h>
 
-/* This assumes that the CBFS resides at start of dram, which is true for the
- * default configuration. */
 static const struct mem_region_device boot_dev =
-	MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE);
+	MEM_REGION_DEV_RO_INIT(QEMU_VIRT_FLASH, CONFIG_ROM_SIZE);
 
 const struct region_device *boot_device_ro(void)
 {
diff --git a/src/mainboard/emulation/qemu-riscv/romstage.c b/src/mainboard/emulation/qemu-riscv/romstage.c
index 4a3ed8304c..39df9ad95d 100644
--- a/src/mainboard/emulation/qemu-riscv/romstage.c
+++ b/src/mainboard/emulation/qemu-riscv/romstage.c
@@ -3,10 +3,20 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <program_loading.h>
+#include <romstage_common.h>
 
-void main(void)
+void __noreturn romstage_main(void)
 {
-	console_init();
 	cbmem_initialize_empty();
 	run_ramstage();
 }
+
+#if CONFIG(SEPARATE_ROMSTAGE)
+
+void main(void)
+{
+	console_init();
+	romstage_main();
+}
+
+#endif