Uwe Hermann:

here's a patch which replaces all DOS newlines with Unix newlines, and removes some useless $Rev$, $Id$, and $Header$ tags. (part 1) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
author: Stefan Reinauer <stepan@openbios.org> 2006-08-23 14:28:37 +0000
committer: Stefan Reinauer <stepan@openbios.org> 2006-08-23 14:28:37 +0000
commit: eca92fb37127246b3c1f323442322e93ed65861d (patch)
tree: 7aca3eaa45135eea56ebde5613e6ac26714ca976 /src
parent: 6a1540b606f55e8b91ac6502af62f1b0c091efe3 (diff)
17 files changed, 995 insertions, 1061 deletions
diff --git a/src/include/assert.h b/src/include/assert.h
index 17f297d62b..4692ed0744 100644
--- a/src/include/assert.h
+++ b/src/include/assert.h
@@ -1,59 +1,51 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/assert.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $
- *
- * assert.h: Debugging macros
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: assert.h,v $
- * Revision 1.1  2005/07/11 16:03:54  smagnani
- * Initial revision.
- *
- *
- */
-
-#ifndef __ASSERT_H_DEFINED
-#define __ASSERT_H_DEFINED
-
-// ROMCC doesn't support __FILE__ or __LINE__  :^{
-
-#if DEBUG
-#ifdef __ROMCC__
-#define ASSERT(x)	{ if (!(x)) die("ASSERT failure!\r\n"); }
-#else
-#define ASSERT(x)	{ 				\
-						if (!(x)) 	\
-						{			\
-							printk_emerg("ASSERT failure: file '%s', line %d\n", __FILE__, __LINE__); \
-							die(""); \
-						}			\
-					}
-#endif		// __ROMCC__
-#else		// !DEBUG
-#define ASSERT(x)	{ }
-#endif
-
-#ifdef __ROMCC__
-#define BUG()		{ 	die("BUG encountered: system halted\r\n");  }
-#else
-#define BUG()		{ 				\
-						printk_emerg("BUG: file '%s', line %d\n", __FILE__, __LINE__); \
-						die(""); \
-					}
-#endif
-					
-#endif 	// __ASSERT_H_DEFINED
+/*
+ * assert.h: Debugging macros
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __ASSERT_H_DEFINED
+#define __ASSERT_H_DEFINED
+
+// ROMCC doesn't support __FILE__ or __LINE__  :^{
+
+#if DEBUG
+#ifdef __ROMCC__
+#define ASSERT(x)	{ if (!(x)) die("ASSERT failure!\r\n"); }
+#else
+#define ASSERT(x)	{ 				\
+						if (!(x)) 	\
+						{			\
+							printk_emerg("ASSERT failure: file '%s', line %d\n", __FILE__, __LINE__); \
+							die(""); \
+						}			\
+					}
+#endif		// __ROMCC__
+#else		// !DEBUG
+#define ASSERT(x)	{ }
+#endif
+
+#ifdef __ROMCC__
+#define BUG()		{ 	die("BUG encountered: system halted\r\n");  }
+#else
+#define BUG()		{ 				\
+						printk_emerg("BUG: file '%s', line %d\n", __FILE__, __LINE__); \
+						die(""); \
+					}
+#endif
+					
+#endif 	// __ASSERT_H_DEFINED
diff --git a/src/include/sdram_mode.h b/src/include/sdram_mode.h
index 238ff6b787..29f3154897 100644
--- a/src/include/sdram_mode.h
+++ b/src/include/sdram_mode.h
@@ -1,62 +1,53 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/sdram_mode.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $
- *
- * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register
- *				 
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: sdram_mode.h,v $
- * Revision 1.1  2005/07/11 16:03:54  smagnani
- * Initial revision.
- *
- *
- */
-
-#ifndef __SDRAMMODE_H_DEFINED
-#define __SDRAMMODE_H_DEFINED
-
-// SDRAM Mode Register definitions, per JESD79D
-// These are transmitted via A0-A13
-
-// Burst length
-#define SDRAM_BURST_2     (1<<0)
-#define SDRAM_BURST_4     (2<<0)
-#define SDRAM_BURST_8     (3<<0)
-
-#define SDRAM_BURST_SEQUENTIAL  (0<<3)
-#define SDRAM_BURST_INTERLEAVED	(1<<3)
-
-#define SDRAM_CAS_2_0	  (2<<4)
-#define SDRAM_CAS_3_0     (3<<4)	/* Optional for DDR 200-333 */
-#define SDRAM_CAS_1_5     (5<<4)	/* Optional */
-#define SDRAM_CAS_2_5     (6<<4)
-#define SDRAM_CAS_MASK    (7<<4)
-
-#define SDRAM_MODE_NORMAL		(0 << 7)
-#define SDRAM_MODE_TEST         (1 << 7)
-#define SDRAM_MODE_DLL_RESET    (2 << 7)
-
-// Extended Mode Register
-
-#define SDRAM_EXTMODE_DLL_ENABLE	(0 << 0)
-#define SDRAM_EXTMODE_DLL_DISABLE	(1 << 0)
-
-#define SDRAM_EXTMODE_DRIVE_NORMAL	(0 << 1)
-#define SDRAM_EXTMODE_DRIVE_WEAK	(1 << 1)	/* Optional */
-
-#endif 	// __SDRAMMODE_H_DEFINED
+/*
+ * sdram_mode.h: Definitions for SDRAM Mode Register and Extended Mode Register
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __SDRAMMODE_H_DEFINED
+#define __SDRAMMODE_H_DEFINED
+
+// SDRAM Mode Register definitions, per JESD79D
+// These are transmitted via A0-A13
+
+// Burst length
+#define SDRAM_BURST_2     (1<<0)
+#define SDRAM_BURST_4     (2<<0)
+#define SDRAM_BURST_8     (3<<0)
+
+#define SDRAM_BURST_SEQUENTIAL  (0<<3)
+#define SDRAM_BURST_INTERLEAVED	(1<<3)
+
+#define SDRAM_CAS_2_0	  (2<<4)
+#define SDRAM_CAS_3_0     (3<<4)	/* Optional for DDR 200-333 */
+#define SDRAM_CAS_1_5     (5<<4)	/* Optional */
+#define SDRAM_CAS_2_5     (6<<4)
+#define SDRAM_CAS_MASK    (7<<4)
+
+#define SDRAM_MODE_NORMAL		(0 << 7)
+#define SDRAM_MODE_TEST         (1 << 7)
+#define SDRAM_MODE_DLL_RESET    (2 << 7)
+
+// Extended Mode Register
+
+#define SDRAM_EXTMODE_DLL_ENABLE	(0 << 0)
+#define SDRAM_EXTMODE_DLL_DISABLE	(1 << 0)
+
+#define SDRAM_EXTMODE_DRIVE_NORMAL	(0 << 1)
+#define SDRAM_EXTMODE_DRIVE_WEAK	(1 << 1)	/* Optional */
+
+#endif 	// __SDRAMMODE_H_DEFINED
diff --git a/src/include/spd.h b/src/include/spd.h
index 65ea9d4af5..5fb6468810 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -1,89 +1,81 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/spd.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $
- *
- * spd.h: Definitions for Serial Presence Detect (SPD) data
- *		  stored on SDRAM modules
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: spd.h,v $
- * Revision 1.1  2005/07/11 16:03:54  smagnani
- * Initial revision.
- *
- *
- */
-
-#ifndef __SPD_H_DEFINED
-#define __SPD_H_DEFINED
-
-// Byte numbers
-#define SPD_MEMORY_TYPE							 2
-#define SPD_NUM_ROWS							 3
-#define SPD_NUM_COLUMNS							 4
-#define SPD_NUM_DIMM_BANKS						 5
-#define SPD_MODULE_DATA_WIDTH_LSB				 6
-#define SPD_MODULE_DATA_WIDTH_MSB				 7
-#define SPD_MODULE_VOLTAGE						 8
-#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX			 9
-#define SPD_DIMM_CONFIG_TYPE					11
-#define	SPD_REFRESH								12
-#define SPD_PRIMARY_DRAM_WIDTH					13
-#define SPD_SUPPORTED_BURST_LENGTHS				16
-#define SPD_NUM_BANKS_PER_DRAM					17
-#define SPD_ACCEPTABLE_CAS_LATENCIES			18
-#define SPD_MODULE_ATTRIBUTES					21
-#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05	23
-#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10	25
-#define SPD_MIN_ROW_PRECHARGE_TIME				27
-#define SPD_MIN_RAS_TO_CAS_DELAY				29
-#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY		30
-#define SPD_ADDRESS_CMD_HOLD					33
-
-
-// SPD_MEMORY_TYPE values
-#define MEMORY_TYPE_SDRAM_DDR	7
-
-// SPD_MODULE_VOLTAGE values
-#define SPD_VOLTAGE_SSTL2		4
-
-// SPD_DIMM_CONFIG_TYPE values
-#define ERROR_SCHEME_NONE		0
-#define ERROR_SCHEME_PARITY		1
-#define ERROR_SCHEME_ECC		2
-
-// SPD_ACCEPTABLE_CAS_LATENCIES values
-#define SPD_CAS_LATENCY_1_0		0x01
-#define SPD_CAS_LATENCY_1_5		0x02
-#define SPD_CAS_LATENCY_2_0		0x04
-#define SPD_CAS_LATENCY_2_5		0x08
-#define SPD_CAS_LATENCY_3_0		0x10
-#define SPD_CAS_LATENCY_3_5		0x20
-#define SPD_CAS_LATENCY_4_0		0x40
-
-// SPD_SUPPORTED_BURST_LENGTHS values
-#define SPD_BURST_LENGTH_1		1
-#define SPD_BURST_LENGTH_2		2
-#define SPD_BURST_LENGTH_4		4
-#define SPD_BURST_LENGTH_8		8
-#define SPD_BURST_LENGTH_PAGE	(1<<7)
-
-
-// SPD_MODULE_ATTRIBUTES values
-#define MODULE_BUFFERED			1
-#define MODULE_REGISTERED		2
-
-#endif 	// __SPD_H_DEFINED
+/*
+ * spd.h: Definitions for Serial Presence Detect (SPD) data
+ *		  stored on SDRAM modules
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __SPD_H_DEFINED
+#define __SPD_H_DEFINED
+
+// Byte numbers
+#define SPD_MEMORY_TYPE							 2
+#define SPD_NUM_ROWS							 3
+#define SPD_NUM_COLUMNS							 4
+#define SPD_NUM_DIMM_BANKS						 5
+#define SPD_MODULE_DATA_WIDTH_LSB				 6
+#define SPD_MODULE_DATA_WIDTH_MSB				 7
+#define SPD_MODULE_VOLTAGE						 8
+#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX			 9
+#define SPD_DIMM_CONFIG_TYPE					11
+#define	SPD_REFRESH								12
+#define SPD_PRIMARY_DRAM_WIDTH					13
+#define SPD_SUPPORTED_BURST_LENGTHS				16
+#define SPD_NUM_BANKS_PER_DRAM					17
+#define SPD_ACCEPTABLE_CAS_LATENCIES			18
+#define SPD_MODULE_ATTRIBUTES					21
+#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_05	23
+#define SPD_MIN_CYCLE_TIME_AT_CAS_REDUCED_10	25
+#define SPD_MIN_ROW_PRECHARGE_TIME				27
+#define SPD_MIN_RAS_TO_CAS_DELAY				29
+#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY		30
+#define SPD_ADDRESS_CMD_HOLD					33
+
+
+// SPD_MEMORY_TYPE values
+#define MEMORY_TYPE_SDRAM_DDR	7
+
+// SPD_MODULE_VOLTAGE values
+#define SPD_VOLTAGE_SSTL2		4
+
+// SPD_DIMM_CONFIG_TYPE values
+#define ERROR_SCHEME_NONE		0
+#define ERROR_SCHEME_PARITY		1
+#define ERROR_SCHEME_ECC		2
+
+// SPD_ACCEPTABLE_CAS_LATENCIES values
+#define SPD_CAS_LATENCY_1_0		0x01
+#define SPD_CAS_LATENCY_1_5		0x02
+#define SPD_CAS_LATENCY_2_0		0x04
+#define SPD_CAS_LATENCY_2_5		0x08
+#define SPD_CAS_LATENCY_3_0		0x10
+#define SPD_CAS_LATENCY_3_5		0x20
+#define SPD_CAS_LATENCY_4_0		0x40
+
+// SPD_SUPPORTED_BURST_LENGTHS values
+#define SPD_BURST_LENGTH_1		1
+#define SPD_BURST_LENGTH_2		2
+#define SPD_BURST_LENGTH_4		4
+#define SPD_BURST_LENGTH_8		8
+#define SPD_BURST_LENGTH_PAGE	(1<<7)
+
+
+// SPD_MODULE_ATTRIBUTES values
+#define MODULE_BUFFERED			1
+#define MODULE_REGISTERED		2
+
+#endif 	// __SPD_H_DEFINED
diff --git a/src/northbridge/intel/e7501/e7501.h b/src/northbridge/intel/e7501/e7501.h
index 707f34789d..6418677f07 100644
--- a/src/northbridge/intel/e7501/e7501.h
+++ b/src/northbridge/intel/e7501/e7501.h
@@ -1,6 +1,4 @@
 /*
- * $Header$
- *
  * e7501.h: PCI configuration space for the Intel E7501 memory controller
  *
  * Copyright (C) 2005 Digital Design Corporation
@@ -18,9 +16,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
  */
 
 
diff --git a/src/southbridge/intel/i82801ca/cmos_failover.c b/src/southbridge/intel/i82801ca/cmos_failover.c
index 6197ef677a..8eb11c3f64 100644
--- a/src/southbridge/intel/i82801ca/cmos_failover.c
+++ b/src/southbridge/intel/i82801ca/cmos_failover.c
@@ -1,19 +1,19 @@
-//kind of cmos_err for ich3
-
-#include "i82801ca.h"
+//kind of cmos_err for ich3
+
+#include "i82801ca.h"
 
 static void check_cmos_failed(void) 
-{
+{
 #if HAVE_OPTION_TABLE
-	uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
+	uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
 
 	if( byte & RTC_BATTERY_DEAD) {
-		// Set boot_option and last_boot to 'Fallback',
+		// Set boot_option and last_boot to 'Fallback',
 		// clear reboot_bits
         byte = cmos_read(RTC_BOOT_BYTE);
         byte &= 0x0c;
         byte |= MAX_REBOOT_CNT << 4;
         cmos_write(byte, RTC_BOOT_BYTE);
-    }
+    }
 #endif
 }
diff --git a/src/southbridge/intel/i82801ca/i82801ca.c b/src/southbridge/intel/i82801ca/i82801ca.c
index 27432d95fb..11ac82c329 100644
--- a/src/southbridge/intel/i82801ca/i82801ca.c
+++ b/src/southbridge/intel/i82801ca/i82801ca.c
@@ -7,8 +7,8 @@
 
 void i82801ca_enable(device_t dev)
 {
-	unsigned int index = 0;
-	uint8_t bHasDisableBit = 0;
+	unsigned int index = 0;
+	uint8_t bHasDisableBit = 0;
 	uint16_t cur_disable_mask, new_disable_mask;
 
 //	all 82801ca devices are in bus 0
@@ -19,22 +19,22 @@ void i82801ca_enable(device_t dev)
 
 	// Calculate disable bit position for specified device:function
 	// NOTE: For ICH-3, only the following devices can be disabled:
-	//		 D31:F1, D31:F3, D31:F5, D31:F6, 
-	//		 D29:F0, D29:F1, D29:F2
+	//		 D31:F1, D31:F3, D31:F5, D31:F6, 
+	//		 D29:F0, D29:F1, D29:F2
 
     if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
-    	index = PCI_FUNC(dev->path.u.pci.devfn);
-
-		if ((index == 1) || (index == 3) || (index == 5) || (index == 6))
-			bHasDisableBit = 1;
+    	index = PCI_FUNC(dev->path.u.pci.devfn);
+
+		if ((index == 1) || (index == 3) || (index == 5) || (index == 6))
+			bHasDisableBit = 1;
 
     } else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
-    	index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
-
-		if (PCI_FUNC(dev->path.u.pci.devfn) < 3)
+    	index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
+
+		if (PCI_FUNC(dev->path.u.pci.devfn) < 3)
 			bHasDisableBit = 1;
     }
-
+
 	if (bHasDisableBit) {
 		cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
 		new_disable_mask = cur_disable_mask & ~(1<<index); 		// enable it
@@ -43,7 +43,7 @@ void i82801ca_enable(device_t dev)
 		}
 		if (new_disable_mask != cur_disable_mask) {
 			pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
-		}
+		}
 	}
 }
 
diff --git a/src/southbridge/intel/i82801ca/i82801ca.h b/src/southbridge/intel/i82801ca/i82801ca.h
index a5117f23b6..59056f29df 100644
--- a/src/southbridge/intel/i82801ca/i82801ca.h
+++ b/src/southbridge/intel/i82801ca/i82801ca.h
@@ -1,10 +1,10 @@
 #ifndef I82801CA_H
 #define I82801CA_H
-
-#ifndef __ROMCC__
+
+#ifndef __ROMCC__
 #include "chip.h"
-extern void i82801ca_enable(device_t dev);
-#endif
+extern void i82801ca_enable(device_t dev);
+#endif
 
 
 #define PCI_DMA_CFG     0x90
@@ -26,37 +26,37 @@ extern void i82801ca_enable(device_t dev);
 #define FUNC_DIS        0xF2
 
 // GEN_PMCON_3 bits
-#define RTC_BATTERY_DEAD		(1<<2)
-#define RTC_POWER_FAILED		(1<<1)
+#define RTC_BATTERY_DEAD		(1<<2)
+#define RTC_POWER_FAILED		(1<<1)
 #define SLEEP_AFTER_POWER_FAIL	(1<<0)
-
-/********************************************************************/
-/*							IDE Controller                          */
-/********************************************************************/
-
-// PCI Configuration Space (D31:F1)
-#define IDE_TIM_PRI		0x40		// IDE timings, primary
-#define IDE_TIM_SEC		0x42		// IDE timings, secondary
-
-
-// IDE_TIM bits
-#define IDE_DECODE_ENABLE	(1<<15)
-
-/********************************************************************/
-/*								SMBus                               */
-/********************************************************************/
-
-// PCI Configuration Space (D31:F3)
+
+/********************************************************************/
+/*							IDE Controller                          */
+/********************************************************************/
+
+// PCI Configuration Space (D31:F1)
+#define IDE_TIM_PRI		0x40		// IDE timings, primary
+#define IDE_TIM_SEC		0x42		// IDE timings, secondary
+
+
+// IDE_TIM bits
+#define IDE_DECODE_ENABLE	(1<<15)
+
+/********************************************************************/
+/*								SMBus                               */
+/********************************************************************/
+
+// PCI Configuration Space (D31:F3)
 #define SMB_BASE	0x20
-#define HOSTC		0x40
-
-// HOSTC bits
-#define I2C_EN		(1<<2)
-#define SMB_SMI_EN	(1<<1)
-#define HST_EN		(1<<0)
+#define HOSTC		0x40
+
+// HOSTC bits
+#define I2C_EN		(1<<2)
+#define SMB_SMI_EN	(1<<1)
+#define HST_EN		(1<<0)
 
 #define SMBUS_IO_BASE 0x1000
-
+
 // I/O registers (relative to SMBUS_IO_BASE)
 #define SMBHSTSTAT		0
 #define SMBHSTCTL		2
@@ -69,7 +69,7 @@ extern void i82801ca_enable(device_t dev);
 #define SMBSLVDATA		10
 #define SMLINK_PIN_CTL	14
 #define SMBUS_PIN_CTL	15 
-
+
 /* Between 1-10 seconds, We should never timeout normally 
  * Longer than this is just painful when a timeout condition occurs.
  */
diff --git a/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c b/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
index 054af75089..c97dd63e2c 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
@@ -1,5 +1,5 @@
 #include <device/pci_ids.h>
-#include "i82801ca.h"
+#include "i82801ca.h"
 
 static void enable_smbus(void)
 {
diff --git a/src/southbridge/intel/i82801ca/i82801ca_ide.c b/src/southbridge/intel/i82801ca/i82801ca_ide.c
index 50539fc5f7..38700bd851 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_ide.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_ide.c
@@ -10,7 +10,7 @@ static void ide_init(struct device *dev)
 {
 	/* Enable ide devices so the linux ide driver will work */
 	uint16_t ideTimingConfig;
-	int enable_primary = 1;
+	int enable_primary = 1;
 	int enable_secondary = 1;
 
 	ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
diff --git a/src/southbridge/intel/i82801ca/i82801ca_lpc.c b/src/southbridge/intel/i82801ca/i82801ca_lpc.c
index 306d01a972..99d6803931 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_lpc.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_lpc.c
@@ -1,7 +1,7 @@
 /*
  * (C) 2003 Linux Networx, SuSE Linux AG
  * (C) 2004 Tyan Computer
- * (c) 2005 Digital Design Corporation
+ * (c) 2005 Digital Design Corporation
  */
 #include <console/console.h>
 #include <device/device.h>
@@ -14,14 +14,14 @@
 #include "i82801ca.h"
 
 #define NMI_OFF 0
-
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON  1
-
+
+#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON  1
+
 
 void i82801ca_enable_ioapic( struct device *dev) 
 {
@@ -60,20 +60,20 @@ void i82801ca_enable_serial_irqs( struct device *dev)
     pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	i82801ca_lpc_route_dma
+//----------------------------------------------------------------------------------
+// Function:    	i82801ca_lpc_route_dma
 // Parameters:  	dev
 //					mask - identifies whether each channel should be used for PCI DMA
 //						   (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
-//						   Channel 4 is not used (reserved). 
-// Return Value:	None
-// Description: 	Route all DMA channels to either PCI or LPC.
-//
+//						   Channel 4 is not used (reserved). 
+// Return Value:	None
+// Description: 	Route all DMA channels to either PCI or LPC.
+//
 void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask) 
 {
     uint16_t dmaConfig;
     int channelIndex;
-
+
     dmaConfig = pci_read_config16(dev, PCI_DMA_CFG);
     dmaConfig &= 0x300;				// Preserve reserved bits
     for(channelIndex = 0; channelIndex < 8; channelIndex++) {
@@ -87,26 +87,26 @@ void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask)
 void i82801ca_rtc_init(struct device *dev)
 {
     uint32_t dword;
-    int rtc_failed;
-	int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
-    uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
+    int rtc_failed;
+	int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+    uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
 
     rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
     if (rtc_failed) {
     	// Clear the RTC_BATTERY_DEAD bit, but preserve
-        // the RTC_POWER_FAILED, G3 state, and reserved bits
+        // the RTC_POWER_FAILED, G3 state, and reserved bits
 		// NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits
         pmcon3 &= ~RTC_POWER_FAILED;
-    }
-
-    get_option(&pwr_on, "power_on_after_fail");
-	pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
-	if (!pwr_on) {
-		pmcon3 |= SLEEP_AFTER_POWER_FAIL;
-	}
-	pci_write_config8(dev, GEN_PMCON_3, pmcon3);
-	printk_info("set power %s after power fail\n", 
-				 pwr_on ? "on" : "off");
+    }
+
+    get_option(&pwr_on, "power_on_after_fail");
+	pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
+	if (!pwr_on) {
+		pmcon3 |= SLEEP_AFTER_POWER_FAIL;
+	}
+	pci_write_config8(dev, GEN_PMCON_3, pmcon3);
+	printk_info("set power %s after power fail\n", 
+				 pwr_on ? "on" : "off");
 
     // See if the Safe Mode jumper is set
     dword = pci_read_config32(dev, GEN_STS);
@@ -142,14 +142,14 @@ void i82801ca_1f0_misc(struct device *dev)
     // Enable access to the upper 128 byte bank of CMOS RAM
     pci_write_config8(dev, RTC_CONF, 0x04);
         
-    // Decode 0x3F8-0x3FF (COM1) for COMA port,
+    // Decode 0x3F8-0x3FF (COM1) for COMA port,
 	//		  0x2F8-0x2FF (COM2) for COMB
     pci_write_config8(dev, COM_DEC, 0x10);
-
-	// LPT decode defaults to 0x378-0x37F and 0x778-0x77F
-	// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
 
-    // Enable COMA, COMB, LPT, floppy; 
+	// LPT decode defaults to 0x378-0x37F and 0x778-0x77F
+	// Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
+
+    // Enable COMA, COMB, LPT, floppy; 
 	// disable microcontroller, Super I/O, sound, gameport
     pci_write_config16(dev, LPC_EN, 0x000F);
 }
@@ -179,18 +179,18 @@ static void lpc_init(struct device *dev)
     pci_write_config8(dev, GEN_PMCON_3, byte);
     printk_info("set power %s after power fail\n", pwr_on?"on":"off");
 
-    /* Set up NMI on errors */
-    byte = inb(0x61);
-    byte &= ~(1 << 3); /* IOCHK# NMI Enable */
-    byte &= ~(1 << 2); /* PCI SERR# Enable */
-    outb(byte, 0x61);
-    byte = inb(0x70);
-    nmi_option = NMI_OFF;
-    get_option(&nmi_option, "nmi");
-    if (nmi_option) {			
-        byte &= ~(1 << 7); /* set NMI */
-        outb(byte, 0x70);
-    }
+    /* Set up NMI on errors */
+    byte = inb(0x61);
+    byte &= ~(1 << 3); /* IOCHK# NMI Enable */
+    byte &= ~(1 << 2); /* PCI SERR# Enable */
+    outb(byte, 0x61);
+    byte = inb(0x70);
+    nmi_option = NMI_OFF;
+    get_option(&nmi_option, "nmi");
+    if (nmi_option) {			
+        byte &= ~(1 << 7); /* set NMI */
+        outb(byte, 0x70);
+    }
 	
 	/* Initialize the real time clock */
 	i82801ca_rtc_init(dev);
diff --git a/src/southbridge/intel/i82801ca/i82801ca_smbus.c b/src/southbridge/intel/i82801ca/i82801ca_smbus.c
index ab95e69e70..0eceba7103 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_smbus.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_smbus.c
@@ -1,7 +1,7 @@
 #include <smbus.h>
 #include <pci.h>
 #include <arch/io.h>
-#include "i82801ca.h"
+#include "i82801ca.h"
 
 #define PM_BUS 0
 #define PM_DEVFN PCI_DEVFN(0x1f,3)
@@ -9,7 +9,7 @@
 void smbus_enable(void)
 {
 	/* iobase addr */
-	pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, 
+	pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, 
 							   SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
 	/* smbus enable */
 	pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN);
diff --git a/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c b/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
index 49ec2c47f8..39444c0d02 100644
--- a/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
+++ b/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
@@ -1,62 +1,57 @@
-/*
- * $Header$
- *
- * lpc47b272_early_serial.c: Pre-RAM driver for SMSC LPC47B272 Super I/O chip
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
- */
+/*
+ * lpc47b272_early_serial.c: Pre-RAM driver for SMSC LPC47B272 Super I/O chip
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
 
 #include <arch/romcc_io.h>
 #include "lpc47b272.h"
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Enable access to the LPC47B272's configuration registers.
-//
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Enable access to the LPC47B272's configuration registers.
+//
 static inline void pnp_enter_conf_state(device_t dev) {
 	unsigned port = dev>>8;
     outb(0x55, port);
-}
+}
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Disable access to the LPC47B272's configuration registers.
-//
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Disable access to the LPC47B272's configuration registers.
+//
 static void pnp_exit_conf_state(device_t dev) {
 	unsigned port = dev>>8;
     outb(0xaa, port);
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	lpc47b272_enable_serial
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47b272.h)
-//					iobase - processor I/O port address to assign to this serial device
-// Return Value:	bool
-// Description: 	Configure the base I/O port of the specified serial device
-//					and enable the serial device.
-//
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_enable_serial
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47b272.h)
+//					iobase - processor I/O port address to assign to this serial device
+// Return Value:	bool
+// Description: 	Configure the base I/O port of the specified serial device
+//					and enable the serial device.
+//
 static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
 {
 	pnp_enter_conf_state(dev);
diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c
index 674fbdcfe4..c3d4f9a929 100644
--- a/src/superio/smsc/lpc47b272/superio.c
+++ b/src/superio/smsc/lpc47b272/superio.c
@@ -1,30 +1,25 @@
-/*
- * $Header$
- *
- * superio.c: RAM driver for SMSC LPC47B272 Super I/O chip
- *
+/*
+ * superio.c: RAM driver for SMSC LPC47B272 Super I/O chip
+ *
  * Copyright 2000  AG Electronics Ltd.
  * Copyright 2003-2004 Linux Networx
  * Copyright 2004 Tyan 
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
- */
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
 
 #include <arch/io.h>
 #include <device/device.h>
@@ -38,16 +33,16 @@
 #include "chip.h"
 #include "lpc47b272.h"
 
-// Forward declarations
-static void enable_dev(device_t dev);
+// Forward declarations
+static void enable_dev(device_t dev);
 void lpc47b272_pnp_set_resources(device_t dev);
 void lpc47b272_pnp_set_resources(device_t dev);
 void lpc47b272_pnp_enable_resources(device_t dev);
 void lpc47b272_pnp_enable(device_t dev);
 static void lpc47b272_init(device_t dev);
 
-static void pnp_enter_conf_state(device_t dev);
-static void pnp_exit_conf_state(device_t dev);
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
 static void dump_pnp_device(device_t dev);
 
 
@@ -73,30 +68,30 @@ static struct pnp_info pnp_dev_info[] = {
         { &ops, LPC47B272_RT,   PNP_IO0, { 0x780, 0 }, },
 };
 
-/**********************************************************************************/
-/*								PUBLIC INTERFACE								  */
-/**********************************************************************************/
-
-//----------------------------------------------------------------------------------
-// Function:    	enable_dev
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Create device structures and allocate resources to devices 
-//					specified in the pnp_dev_info array (above).
-//
-static void enable_dev(device_t dev)
-{
-	pnp_enable_devices(dev, &pnp_ops, 
-					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
-					   pnp_dev_info);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47b272_pnp_set_resources
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Configure the specified Super I/O device with the resources
-//					(I/O space, etc.) that have been allocated for it.
+/**********************************************************************************/
+/*								PUBLIC INTERFACE								  */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function:    	enable_dev
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Create device structures and allocate resources to devices 
+//					specified in the pnp_dev_info array (above).
+//
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &pnp_ops, 
+					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
+					   pnp_dev_info);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_pnp_set_resources
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Configure the specified Super I/O device with the resources
+//					(I/O space, etc.) that have been allocated for it.
 //
 void lpc47b272_pnp_set_resources(device_t dev)
 {
@@ -126,14 +121,14 @@ void lpc47b272_pnp_enable(device_t dev)
 	pnp_exit_conf_state(dev);  
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	lpc47b272_init
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Initialize the specified Super I/O device.
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_init
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Initialize the specified Super I/O device.
 //					Devices other than COM ports and the keyboard controller are 
-//					ignored. For COM ports, we configure the baud rate. 
-//
+//					ignored. For COM ports, we configure the baud rate. 
+//
 static void lpc47b272_init(device_t dev)
 {
 	struct superio_smsc_lpc47b272_config *conf = dev->chip_info;
@@ -160,68 +155,68 @@ static void lpc47b272_init(device_t dev)
 		break;
 	}
 }
-
-/**********************************************************************************/
-/*								PRIVATE FUNCTIONS							      */
-/**********************************************************************************/
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Enable access to the LPC47B272's configuration registers.
-//
-static void pnp_enter_conf_state(device_t dev) 
+
+/**********************************************************************************/
+/*								PRIVATE FUNCTIONS							      */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Enable access to the LPC47B272's configuration registers.
+//
+static void pnp_enter_conf_state(device_t dev) 
 {
 	outb(0x55, dev->path.u.pnp.port);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Disable access to the LPC47B272's configuration registers.
-//
-static void pnp_exit_conf_state(device_t dev) 
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Disable access to the LPC47B272's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev) 
 {
     outb(0xaa, dev->path.u.pnp.port);
 }
 
 #if 0
-//----------------------------------------------------------------------------------
-// Function:    	dump_pnp_device
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Print the values of all of the LPC47B272's configuration registers.
-//					NOTE: The LPC47B272 must be in configuration mode when this
-//						  function is called.
-//
+//----------------------------------------------------------------------------------
+// Function:    	dump_pnp_device
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Print the values of all of the LPC47B272's configuration registers.
+//					NOTE: The LPC47B272 must be in configuration mode when this
+//						  function is called.
+//
 static void dump_pnp_device(device_t dev)
 {
     int register_index;
     print_debug("\r\n");
 
     for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) {
-        uint8_t register_value;
+        uint8_t register_value;
 
         if ((register_index & 0x0f) == 0) {
                 print_debug_hex8(register_index);
                 print_debug_char(':');
-        }
-
+        }
+
 		// Skip over 'register' that would cause exit from configuration mode
 	    if (register_index == 0xaa)
-			register_value = 0xaa;
+			register_value = 0xaa;
 		else
-        	register_value = pnp_read_config(dev, register_index);
-
+        	register_value = pnp_read_config(dev, register_index);
+
         print_debug_char(' ');
         print_debug_hex8(register_value);
         if ((register_index & 0x0f) == 0x0f) {
         	print_debug("\r\n");
         }
-    }
-
-   	print_debug("\r\n");
+    }
+
+   	print_debug("\r\n");
 }
 #endif
diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c b/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
index 013453a9f4..70f7b20174 100644
--- a/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
+++ b/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
@@ -1,63 +1,58 @@
-/*
- * $Header$
- *
- * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
+/*
+ * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
  * derived from lpc47n217
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
- */
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
 
 #include <arch/romcc_io.h>
 #include "lpc47m10x.h"
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Enable access to the LPC47M10X2's configuration registers.
-//
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Enable access to the LPC47M10X2's configuration registers.
+//
 static inline void pnp_enter_conf_state(device_t dev) {
 	unsigned port = dev>>8;
     outb(0x55, port);
-}
+}
 
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Disable access to the LPC47M10X2's configuration registers.
-//
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Disable access to the LPC47M10X2's configuration registers.
+//
 static void pnp_exit_conf_state(device_t dev) {
 	unsigned port = dev>>8;
     outb(0xaa, port);
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	lpc47b272_enable_serial
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47b272.h)
-//					iobase - processor I/O port address to assign to this serial device
-// Return Value:	bool
-// Description: 	Configure the base I/O port of the specified serial device
-//					and enable the serial device.
-//
+//----------------------------------------------------------------------------------
+// Function:    	lpc47b272_enable_serial
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47b272.h)
+//					iobase - processor I/O port address to assign to this serial device
+// Return Value:	bool
+// Description: 	Configure the base I/O port of the specified serial device
+//					and enable the serial device.
+//
 static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
 {
 	pnp_enter_conf_state(dev);
diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c
index 05449bd97d..d808514bec 100644
--- a/src/superio/smsc/lpc47m10x/superio.c
+++ b/src/superio/smsc/lpc47m10x/superio.c
@@ -1,6 +1,4 @@
 /*
- * $Header$
- *
  * superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip
  *
  * Copyright 2000  AG Electronics Ltd.
@@ -22,9 +20,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log$
- *
  */
 
 #include <arch/io.h>
diff --git a/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c b/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c
index d3be378065..ae7c2a73a5 100644
--- a/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c
+++ b/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c
@@ -1,155 +1,147 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $
- *
- * lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: lpc47n217_early_serial.c,v $
- * Revision 1.1.1.1  2005/07/11 15:28:51  smagnani
- * Initial revision.
- *
- *
- */
-
-#include <arch/romcc_io.h>
-#include <assert.h>
-#include "lpc47n217.h"
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Enable access to the LPC47N217's configuration registers.
-//
-static inline void pnp_enter_conf_state(device_t dev) {
-	unsigned port = dev>>8;
-    outb(0x55, port);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - high 8 bits = Super I/O port
-// Return Value:	None
-// Description: 	Disable access to the LPC47N217's configuration registers.
-//
-static void pnp_exit_conf_state(device_t dev) {
-	unsigned port = dev>>8;
-    outb(0xaa, port);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_pnp_set_iobase
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47n217.h)
-//					iobase - base I/O port for the logical device
-// Return Value:	None
-// Description: 	Program the base I/O port for the specified logical device.
-//
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
-{
-	// LPC47N217 requires base ports to be a multiple of 4
-	ASSERT(!(iobase & 0x3));
-
-	switch(dev & 0xFF) {
-	case LPC47N217_PP: 
-		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
-		break;
-		
-	case LPC47N217_SP1: 
-		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
-		break;
-		
-	case LPC47N217_SP2:
-		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
-		break;
-		
-	default:
-		break;
-	}
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_pnp_set_enable
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47n217.h)
-//					enable - 0 to disable, anythig else to enable
-// Return Value:	None
-// Description: 	Enable or disable the specified logical device.
-//					Technically, a full disable requires setting the device's base
-//					I/O port below 0x100. We don't do that here, because we don't
-//					have access to a data structure that specifies what the 'real'
-//					base port is (when asked to enable the device). Also the function
-//					is used only to disable the device while its true base port is
-//					programmed (see lpc47n217_enable_serial() below).
-//
-void lpc47n217_pnp_set_enable(device_t dev, int enable)
-{
-	uint8_t power_register = 0;
-	uint8_t power_mask = 0;
-	uint8_t current_power;
-	uint8_t new_power;
-	
-	switch(dev & 0xFF) {
-	case LPC47N217_PP: 
-		power_register = 0x01;
-		power_mask = 0x04;
-		break;
-		
-	case LPC47N217_SP1: 
-		power_register = 0x02;
-		power_mask = 0x08;
-		break;
-		
-	case LPC47N217_SP2:
-		power_register = 0x02;
-		power_mask = 0x80;
-		break;
-		
-	default:
-		return;
-	}
-
-	current_power = pnp_read_config(dev, power_register);
-	new_power = current_power & ~power_mask;		// disable by default
-
-	if (enable)
-		new_power |= power_mask;		// Enable
-
-	pnp_write_config(dev, power_register, new_power);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_enable_serial
-// Parameters:  	dev - high 8 bits = Super I/O port, 
-//						  low 8 bits = logical device number (per lpc47n217.h)
-//					iobase - processor I/O port address to assign to this serial device
-// Return Value:	bool
-// Description: 	Configure the base I/O port of the specified serial device
-//					and enable the serial device.
-//
-static void lpc47n217_enable_serial(device_t dev, unsigned iobase)
-{
-	// NOTE: Cannot use pnp_set_XXX() here because they assume chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-	
-	pnp_enter_conf_state(dev);
-	lpc47n217_pnp_set_enable(dev, 0);
-	lpc47n217_pnp_set_iobase(dev, iobase);
-	lpc47n217_pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
+/*
+ * lpc47n217_early_serial.c: Pre-RAM driver for SMSC LPC47N217 Super I/O chip
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <arch/romcc_io.h>
+#include <assert.h>
+#include "lpc47n217.h"
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Enable access to the LPC47N217's configuration registers.
+//
+static inline void pnp_enter_conf_state(device_t dev) {
+	unsigned port = dev>>8;
+    outb(0x55, port);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - high 8 bits = Super I/O port
+// Return Value:	None
+// Description: 	Disable access to the LPC47N217's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev) {
+	unsigned port = dev>>8;
+    outb(0xaa, port);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_pnp_set_iobase
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47n217.h)
+//					iobase - base I/O port for the logical device
+// Return Value:	None
+// Description: 	Program the base I/O port for the specified logical device.
+//
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
+{
+	// LPC47N217 requires base ports to be a multiple of 4
+	ASSERT(!(iobase & 0x3));
+
+	switch(dev & 0xFF) {
+	case LPC47N217_PP: 
+		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
+		break;
+		
+	case LPC47N217_SP1: 
+		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
+		break;
+		
+	case LPC47N217_SP2:
+		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
+		break;
+		
+	default:
+		break;
+	}
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_pnp_set_enable
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47n217.h)
+//					enable - 0 to disable, anythig else to enable
+// Return Value:	None
+// Description: 	Enable or disable the specified logical device.
+//					Technically, a full disable requires setting the device's base
+//					I/O port below 0x100. We don't do that here, because we don't
+//					have access to a data structure that specifies what the 'real'
+//					base port is (when asked to enable the device). Also the function
+//					is used only to disable the device while its true base port is
+//					programmed (see lpc47n217_enable_serial() below).
+//
+void lpc47n217_pnp_set_enable(device_t dev, int enable)
+{
+	uint8_t power_register = 0;
+	uint8_t power_mask = 0;
+	uint8_t current_power;
+	uint8_t new_power;
+	
+	switch(dev & 0xFF) {
+	case LPC47N217_PP: 
+		power_register = 0x01;
+		power_mask = 0x04;
+		break;
+		
+	case LPC47N217_SP1: 
+		power_register = 0x02;
+		power_mask = 0x08;
+		break;
+		
+	case LPC47N217_SP2:
+		power_register = 0x02;
+		power_mask = 0x80;
+		break;
+		
+	default:
+		return;
+	}
+
+	current_power = pnp_read_config(dev, power_register);
+	new_power = current_power & ~power_mask;		// disable by default
+
+	if (enable)
+		new_power |= power_mask;		// Enable
+
+	pnp_write_config(dev, power_register, new_power);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_enable_serial
+// Parameters:  	dev - high 8 bits = Super I/O port, 
+//						  low 8 bits = logical device number (per lpc47n217.h)
+//					iobase - processor I/O port address to assign to this serial device
+// Return Value:	bool
+// Description: 	Configure the base I/O port of the specified serial device
+//					and enable the serial device.
+//
+static void lpc47n217_enable_serial(device_t dev, unsigned iobase)
+{
+	// NOTE: Cannot use pnp_set_XXX() here because they assume chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+	
+	pnp_enter_conf_state(dev);
+	lpc47n217_pnp_set_enable(dev, 0);
+	lpc47n217_pnp_set_iobase(dev, iobase);
+	lpc47n217_pnp_set_enable(dev, 1);
+	pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c
index 362f257fac..419b3babeb 100644
--- a/src/superio/smsc/lpc47n217/superio.c
+++ b/src/superio/smsc/lpc47n217/superio.c
@@ -1,394 +1,386 @@
-/*
- * $Header: /home/cvs/BIR/ca-cpu/freebios/src/superio/smsc/lpc47n217/superio.c,v 1.1.1.1 2005/07/11 15:28:51 smagnani Exp $
- *
- * superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip
- *
- * Based on LinuxBIOS code for SMSC 47B397:
- * Copyright 2000  AG Electronics Ltd.
- * Copyright 2003-2004 Linux Networx
- * Copyright 2004 Tyan 
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- * $Log: superio.c,v $
- * Revision 1.1.1.1  2005/07/11 15:28:51  smagnani
- * Initial revision.
- *
- *
- */
-
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pnp.h>
-#include <console/console.h>
-#include <device/smbus.h>
-#include <string.h>
-#include <bitops.h>
-#include <uart8250.h>
-#include <assert.h>
-#include "chip.h"
-#include "lpc47n217.h"
-
-// Forward declarations
-static void enable_dev(device_t dev);
-void lpc47n217_pnp_set_resources(device_t dev);
-void lpc47n217_pnp_enable_resources(device_t dev);
-void lpc47n217_pnp_enable(device_t dev);
-static void lpc47n217_init(device_t dev);
-
-static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
-void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);
-void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);
-void lpc47n217_pnp_set_enable(device_t dev, int enable);
-
-static void pnp_enter_conf_state(device_t dev);
-static void pnp_exit_conf_state(device_t dev);
-
-
-struct chip_operations superio_smsc_lpc47n217_ops = {
-	CHIP_NAME("smsc lpc47n217")
-	.enable_dev = enable_dev,
-};
-
-static struct device_operations ops = {
-	.read_resources   = pnp_read_resources,
-	.set_resources    = lpc47n217_pnp_set_resources,
-	.enable_resources = lpc47n217_pnp_enable_resources,
-	.enable           = lpc47n217_pnp_enable,
-	.init             = lpc47n217_init,
-};
-
-static struct pnp_info pnp_dev_info[] = {
-        { &ops, LPC47N217_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-        { &ops, LPC47N217_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-        { &ops, LPC47N217_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }
-};
-
-/**********************************************************************************/
-/*								PUBLIC INTERFACE								  */
-/**********************************************************************************/
-
-//----------------------------------------------------------------------------------
-// Function:    	enable_dev
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Create device structures and allocate resources to devices 
-//					specified in the pnp_dev_info array (above).
-//
-static void enable_dev(device_t dev)
-{
-	pnp_enable_devices(dev, &pnp_ops, 
-					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
-					   pnp_dev_info);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_pnp_set_resources
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Configure the specified Super I/O device with the resources
-//					(I/O space, etc.) that have been allocate for it.
-//
-void lpc47n217_pnp_set_resources(device_t dev)
-{
-	int i;
-	
-	pnp_enter_conf_state(dev);  
-
-	// NOTE: Cannot use pnp_set_resources() here because it assumes chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-	for(i = 0; i < dev->resources; i++)
-		lpc47n217_pnp_set_resource(dev, &dev->resource[i]);
-
-//	dump_pnp_device(dev);
-                
-   	pnp_exit_conf_state(dev);  
-}       
-
-void lpc47n217_pnp_enable_resources(device_t dev)
-{       
-    pnp_enter_conf_state(dev);
-
-	// NOTE: Cannot use pnp_enable_resources() here because it assumes chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-    lpc47n217_pnp_set_enable(dev, 1);
-
-    pnp_exit_conf_state(dev);
-}
-
-void lpc47n217_pnp_enable(device_t dev)
-{
-	pnp_enter_conf_state(dev);   
-
-	// NOTE: Cannot use pnp_set_enable() here because it assumes chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-
-	if(dev->enabled) {
-		lpc47n217_pnp_set_enable(dev, 1);
-	}
-	else {
-		lpc47n217_pnp_set_enable(dev, 0);
-	}
-
-	pnp_exit_conf_state(dev);  
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	lpc47n217_init
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Initialize the specified Super I/O device.
-//					Devices other than COM ports are ignored.
-//					For COM ports, we configure the baud rate. 
-//
-static void lpc47n217_init(device_t dev)
-{
-	struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
-	struct resource *res0;
-
-	if (!dev->enabled)
-		return;
-
-	switch(dev->path.u.pnp.device) {
-	case LPC47N217_SP1: 
-		res0 = find_resource(dev, PNP_IDX_IO0);
-		init_uart8250(res0->base, &conf->com1);
-		break;
-
-	case LPC47N217_SP2:
-		res0 = find_resource(dev, PNP_IDX_IO0);
-		init_uart8250(res0->base, &conf->com2);
-		break;
-	}
-}
-
-
-/**********************************************************************************/
-/*								PRIVATE FUNCTIONS							      */
-/**********************************************************************************/
-
-static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
-{
-	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk_err("ERROR: %s %02x not allocated\n",
-			dev_path(dev), resource->index);
-		return;
-	}
-
-	/* Now store the resource */
-	// NOTE: Cannot use pnp_set_XXX() here because they assume chip
-	//		 support for logical devices, which the LPC47N217 doesn't have
-
-	if (resource->flags & IORESOURCE_IO) {
-		lpc47n217_pnp_set_iobase(dev, resource->base);
-	}
-	else if (resource->flags & IORESOURCE_DRQ) {
-		lpc47n217_pnp_set_drq(dev, resource->base);
-	}
-	else if (resource->flags  & IORESOURCE_IRQ) {
-		lpc47n217_pnp_set_irq(dev, resource->base);
-	}
-	else {
-		printk_err("ERROR: %s %02x unknown resource type\n",
-			dev_path(dev), resource->index);
-		return;
-	}
-	resource->flags |= IORESOURCE_STORED;
-
-	report_resource_stored(dev, resource, "");
-}
-
-void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
-{
-	ASSERT(!(iobase & 0x3));
-	
-	switch(dev->path.u.pnp.device) {
-	case LPC47N217_PP: 
-		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
-		break;
-		
-	case LPC47N217_SP1: 
-		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
-		break;
-		
-	case LPC47N217_SP2:
-		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
-		break;
-		
-	default:
-		BUG();
-		break;
-	}
-}
-
-void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
-{
-	if (dev->path.u.pnp.device == LPC47N217_PP) {
-		const uint8_t PP_DMA_MASK = 0x0F;
-		const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
-		uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
-		uint8_t new_config;
-
-		ASSERT(!(drq & ~PP_DMA_MASK));		// DRQ out of range??		
-		new_config = (current_config & ~PP_DMA_MASK) | drq;
-		pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
-	} else {
-		BUG();
-	}
-}
-
-void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
-{
-	uint8_t irq_config_register = 0;
-	uint8_t irq_config_mask = 0;
-	uint8_t current_config;
-	uint8_t new_config;
-	
-	switch(dev->path.u.pnp.device) {
-	case LPC47N217_PP: 
-		irq_config_register = 0x27;
-		irq_config_mask = 0x0F;
-		break;
-		
-	case LPC47N217_SP1: 
-		irq_config_register = 0x28;
-		irq_config_mask = 0xF0;
-		irq <<= 4;
-		break;
-		
-	case LPC47N217_SP2:
-		irq_config_register = 0x28;
-		irq_config_mask = 0x0F;
-		break;
-		
-	default:
-		BUG();
-		return;
-	}
-
-	ASSERT(!(irq & ~irq_config_mask));		// IRQ out of range??
-	
-	current_config = pnp_read_config(dev, irq_config_register);
-	new_config = (current_config & ~irq_config_mask) | irq;
-	pnp_write_config(dev, irq_config_register, new_config);
-}
-
-void lpc47n217_pnp_set_enable(device_t dev, int enable)
-{
-	uint8_t power_register = 0;
-	uint8_t power_mask = 0;
-	uint8_t current_power;
-	uint8_t new_power;
-	
-	switch(dev->path.u.pnp.device) {
-	case LPC47N217_PP: 
-		power_register = 0x01;
-		power_mask = 0x04;
-		break;
-		
-	case LPC47N217_SP1: 
-		power_register = 0x02;
-		power_mask = 0x08;
-		break;
-		
-	case LPC47N217_SP2:
-		power_register = 0x02;
-		power_mask = 0x80;
-		break;
-		
-	default:
-		BUG();
-		return;
-	}
-
-	current_power = pnp_read_config(dev, power_register);
-	new_power = current_power & ~power_mask;		// disable by default
-
-	if (enable) {
-		struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);
-		lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
-		
-		new_power |= power_mask;		// Enable
-		
-    } else {
-		lpc47n217_pnp_set_iobase(dev, 0);
-	}
-	pnp_write_config(dev, power_register, new_power);
-}
-
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_enter_conf_state
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Enable access to the LPC47N217's configuration registers.
-//
-static void pnp_enter_conf_state(device_t dev) 
-{
-	outb(0x55, dev->path.u.pnp.port);
-}
-
-//----------------------------------------------------------------------------------
-// Function:    	pnp_exit_conf_state
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Disable access to the LPC47N217's configuration registers.
-//
-static void pnp_exit_conf_state(device_t dev) 
-{
-    outb(0xaa, dev->path.u.pnp.port);
-}
-
-#if 0
-//----------------------------------------------------------------------------------
-// Function:    	dump_pnp_device
-// Parameters:  	dev - pointer to structure describing a Super I/O device 
-// Return Value:	None
-// Description: 	Print the values of all of the LPC47N217's configuration registers.
-//					NOTE: The LPC47N217 must be in configuration mode when this
-//						  function is called.
-//
-static void dump_pnp_device(device_t dev)
-{
-    int register_index;
-    print_debug("\r\n");
-
-    for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
-        uint8_t register_value;
-
-        if ((register_index & 0x0f) == 0) {
-                print_debug_hex8(register_index);
-                print_debug_char(':');
-        }
-
-		// Skip over 'register' that would cause exit from configuration mode
-	    if (register_index == 0xaa)
-			register_value = 0xaa;
-		else
-        	register_value = pnp_read_config(dev, register_index);
-
-        print_debug_char(' ');
-        print_debug_hex8(register_value);
-        if ((register_index & 0x0f) == 0x0f) {
-        	print_debug("\r\n");
-        }
-    }
-
-   	print_debug("\r\n");
-}
-#endif
+/*
+ * superio.c: RAM-based driver for SMSC LPC47N217 Super I/O chip
+ *
+ * Based on LinuxBIOS code for SMSC 47B397:
+ * Copyright 2000  AG Electronics Ltd.
+ * Copyright 2003-2004 Linux Networx
+ * Copyright 2004 Tyan 
+ *
+ * Copyright (C) 2005 Digital Design Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <assert.h>
+#include "chip.h"
+#include "lpc47n217.h"
+
+// Forward declarations
+static void enable_dev(device_t dev);
+void lpc47n217_pnp_set_resources(device_t dev);
+void lpc47n217_pnp_enable_resources(device_t dev);
+void lpc47n217_pnp_enable(device_t dev);
+static void lpc47n217_init(device_t dev);
+
+static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
+void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);
+void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);
+void lpc47n217_pnp_set_enable(device_t dev, int enable);
+
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
+
+
+struct chip_operations superio_smsc_lpc47n217_ops = {
+	CHIP_NAME("smsc lpc47n217")
+	.enable_dev = enable_dev,
+};
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = lpc47n217_pnp_set_resources,
+	.enable_resources = lpc47n217_pnp_enable_resources,
+	.enable           = lpc47n217_pnp_enable,
+	.init             = lpc47n217_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+        { &ops, LPC47N217_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+        { &ops, LPC47N217_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+        { &ops, LPC47N217_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }
+};
+
+/**********************************************************************************/
+/*								PUBLIC INTERFACE								  */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function:    	enable_dev
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Create device structures and allocate resources to devices 
+//					specified in the pnp_dev_info array (above).
+//
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &pnp_ops, 
+					   sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), 
+					   pnp_dev_info);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_pnp_set_resources
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Configure the specified Super I/O device with the resources
+//					(I/O space, etc.) that have been allocate for it.
+//
+void lpc47n217_pnp_set_resources(device_t dev)
+{
+	int i;
+	
+	pnp_enter_conf_state(dev);  
+
+	// NOTE: Cannot use pnp_set_resources() here because it assumes chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+	for(i = 0; i < dev->resources; i++)
+		lpc47n217_pnp_set_resource(dev, &dev->resource[i]);
+
+//	dump_pnp_device(dev);
+                
+   	pnp_exit_conf_state(dev);  
+}       
+
+void lpc47n217_pnp_enable_resources(device_t dev)
+{       
+    pnp_enter_conf_state(dev);
+
+	// NOTE: Cannot use pnp_enable_resources() here because it assumes chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+    lpc47n217_pnp_set_enable(dev, 1);
+
+    pnp_exit_conf_state(dev);
+}
+
+void lpc47n217_pnp_enable(device_t dev)
+{
+	pnp_enter_conf_state(dev);   
+
+	// NOTE: Cannot use pnp_set_enable() here because it assumes chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+
+	if(dev->enabled) {
+		lpc47n217_pnp_set_enable(dev, 1);
+	}
+	else {
+		lpc47n217_pnp_set_enable(dev, 0);
+	}
+
+	pnp_exit_conf_state(dev);  
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	lpc47n217_init
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Initialize the specified Super I/O device.
+//					Devices other than COM ports are ignored.
+//					For COM ports, we configure the baud rate. 
+//
+static void lpc47n217_init(device_t dev)
+{
+	struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
+	struct resource *res0;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.u.pnp.device) {
+	case LPC47N217_SP1: 
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+
+	case LPC47N217_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	}
+}
+
+
+/**********************************************************************************/
+/*								PRIVATE FUNCTIONS							      */
+/**********************************************************************************/
+
+static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
+{
+	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+		printk_err("ERROR: %s %02x not allocated\n",
+			dev_path(dev), resource->index);
+		return;
+	}
+
+	/* Now store the resource */
+	// NOTE: Cannot use pnp_set_XXX() here because they assume chip
+	//		 support for logical devices, which the LPC47N217 doesn't have
+
+	if (resource->flags & IORESOURCE_IO) {
+		lpc47n217_pnp_set_iobase(dev, resource->base);
+	}
+	else if (resource->flags & IORESOURCE_DRQ) {
+		lpc47n217_pnp_set_drq(dev, resource->base);
+	}
+	else if (resource->flags  & IORESOURCE_IRQ) {
+		lpc47n217_pnp_set_irq(dev, resource->base);
+	}
+	else {
+		printk_err("ERROR: %s %02x unknown resource type\n",
+			dev_path(dev), resource->index);
+		return;
+	}
+	resource->flags |= IORESOURCE_STORED;
+
+	report_resource_stored(dev, resource, "");
+}
+
+void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
+{
+	ASSERT(!(iobase & 0x3));
+	
+	switch(dev->path.u.pnp.device) {
+	case LPC47N217_PP: 
+		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
+		break;
+		
+	case LPC47N217_SP1: 
+		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
+		break;
+		
+	case LPC47N217_SP2:
+		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
+		break;
+		
+	default:
+		BUG();
+		break;
+	}
+}
+
+void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
+{
+	if (dev->path.u.pnp.device == LPC47N217_PP) {
+		const uint8_t PP_DMA_MASK = 0x0F;
+		const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
+		uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
+		uint8_t new_config;
+
+		ASSERT(!(drq & ~PP_DMA_MASK));		// DRQ out of range??		
+		new_config = (current_config & ~PP_DMA_MASK) | drq;
+		pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
+	} else {
+		BUG();
+	}
+}
+
+void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
+{
+	uint8_t irq_config_register = 0;
+	uint8_t irq_config_mask = 0;
+	uint8_t current_config;
+	uint8_t new_config;
+	
+	switch(dev->path.u.pnp.device) {
+	case LPC47N217_PP: 
+		irq_config_register = 0x27;
+		irq_config_mask = 0x0F;
+		break;
+		
+	case LPC47N217_SP1: 
+		irq_config_register = 0x28;
+		irq_config_mask = 0xF0;
+		irq <<= 4;
+		break;
+		
+	case LPC47N217_SP2:
+		irq_config_register = 0x28;
+		irq_config_mask = 0x0F;
+		break;
+		
+	default:
+		BUG();
+		return;
+	}
+
+	ASSERT(!(irq & ~irq_config_mask));		// IRQ out of range??
+	
+	current_config = pnp_read_config(dev, irq_config_register);
+	new_config = (current_config & ~irq_config_mask) | irq;
+	pnp_write_config(dev, irq_config_register, new_config);
+}
+
+void lpc47n217_pnp_set_enable(device_t dev, int enable)
+{
+	uint8_t power_register = 0;
+	uint8_t power_mask = 0;
+	uint8_t current_power;
+	uint8_t new_power;
+	
+	switch(dev->path.u.pnp.device) {
+	case LPC47N217_PP: 
+		power_register = 0x01;
+		power_mask = 0x04;
+		break;
+		
+	case LPC47N217_SP1: 
+		power_register = 0x02;
+		power_mask = 0x08;
+		break;
+		
+	case LPC47N217_SP2:
+		power_register = 0x02;
+		power_mask = 0x80;
+		break;
+		
+	default:
+		BUG();
+		return;
+	}
+
+	current_power = pnp_read_config(dev, power_register);
+	new_power = current_power & ~power_mask;		// disable by default
+
+	if (enable) {
+		struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);
+		lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
+		
+		new_power |= power_mask;		// Enable
+		
+    } else {
+		lpc47n217_pnp_set_iobase(dev, 0);
+	}
+	pnp_write_config(dev, power_register, new_power);
+}
+
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_enter_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Enable access to the LPC47N217's configuration registers.
+//
+static void pnp_enter_conf_state(device_t dev) 
+{
+	outb(0x55, dev->path.u.pnp.port);
+}
+
+//----------------------------------------------------------------------------------
+// Function:    	pnp_exit_conf_state
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Disable access to the LPC47N217's configuration registers.
+//
+static void pnp_exit_conf_state(device_t dev) 
+{
+    outb(0xaa, dev->path.u.pnp.port);
+}
+
+#if 0
+//----------------------------------------------------------------------------------
+// Function:    	dump_pnp_device
+// Parameters:  	dev - pointer to structure describing a Super I/O device 
+// Return Value:	None
+// Description: 	Print the values of all of the LPC47N217's configuration registers.
+//					NOTE: The LPC47N217 must be in configuration mode when this
+//						  function is called.
+//
+static void dump_pnp_device(device_t dev)
+{
+    int register_index;
+    print_debug("\r\n");
+
+    for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
+        uint8_t register_value;
+
+        if ((register_index & 0x0f) == 0) {
+                print_debug_hex8(register_index);
+                print_debug_char(':');
+        }
+
+		// Skip over 'register' that would cause exit from configuration mode
+	    if (register_index == 0xaa)
+			register_value = 0xaa;
+		else
+        	register_value = pnp_read_config(dev, register_index);
+
+        print_debug_char(' ');
+        print_debug_hex8(register_value);
+        if ((register_index & 0x0f) == 0x0f) {
+        	print_debug("\r\n");
+        }
+    }
+
+   	print_debug("\r\n");
+}
+#endif
author	Stefan Reinauer <stepan@openbios.org>	2006-08-23 14:28:37 +0000
committer	Stefan Reinauer <stepan@openbios.org>	2006-08-23 14:28:37 +0000
commit	eca92fb37127246b3c1f323442322e93ed65861d (patch)
tree	7aca3eaa45135eea56ebde5613e6ac26714ca976 /src
parent	6a1540b606f55e8b91ac6502af62f1b0c091efe3 (diff)