diff options
| author | Chris.Wang <chris.wang@amd.corp-partner.google.com> | 2022-04-01 14:53:39 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-06 17:41:41 +0000 |
| commit | ec7a932aa291e228d629be2d5d273fe625643588 (patch) | |
| tree | 0496605d805aa73f1ede069e1f88717885073773 /src | |
| parent | 4fdd84e716bb052bfbae58366c687be2656a97bb (diff) | |
mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device
Setting the clock source depends on clock request pin for WLAN/SD/SSD
device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim,
clock source 0/1/2 are routed for WLAN/SD/SSD device.
BUG=b:227297986
BRANCH=none
TEST=Build
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/baseboard/devicetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 7f74d6d6fd..a6894eefa4 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -47,6 +47,12 @@ chip soc/amd/sabrina register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC + # general purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works device domain 0 on |