diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-24 13:52:39 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-27 03:01:48 +0000 |
| commit | eab9e867330ad55374de283445b65c67ddab941b (patch) | |
| tree | 656b542e0e95ee9ccb1cc62653820cfd4666e808 /src | |
| parent | 8c0dda218391afb95444d180333e552ba347aba7 (diff) | |
soc/intel/icelake: Use GPIO state macros from intelblocks/gpio_defs.h
TEST=Able to build and boot ICLRVP platform.
1) Dump and disassemble DSDT to ensure GRXS function implementation
remain unchanged prior and after this CL.
2) Verify no ACPI error seen while running 'dmesg' from console.
3) abuild --timeless to ensure there are no other functional changes.
Change-Id: Iab4690341bc3da5d8eb249da4d407d84f7d4e706
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/icelake/acpi/gpio.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/icelake/include/soc/gpio_defs.h | 2 |
2 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/intel/icelake/acpi/gpio.asl b/src/soc/intel/icelake/acpi/gpio.asl index f0a6fa064c..a00521ac3c 100644 --- a/src/soc/intel/icelake/acpi/gpio.asl +++ b/src/soc/intel/icelake/acpi/gpio.asl @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/gpio_defs.h> #include <soc/gpio_defs.h> #include <soc/irq.h> #include <soc/pcr_ids.h> @@ -114,7 +115,7 @@ Method (GRXS, 1, Serialized) { VAL0, 32 } - Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT) + Local0 = (PAD_CFG0_RX_STATE & VAL0) >> PAD_CFG0_RX_STATE_BIT Return (Local0) } diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index 57701e1ec6..577ca5f427 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -257,6 +257,4 @@ #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 -#define GPIORXSTATE_MASK 0x1 -#define GPIORXSTATE_SHIFT 1 #endif |