mips: add coherency argument to identity mapping

In order for a U-boot payload to work properly the soc_registers
region (device registers) needs to be mapped as uncached.
Therefore, add a coherency argument to the identity mapping funcion
which will establish the type of mapping.

Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12769
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

4 files changed, 22 insertions, 12 deletions

diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h
index 10fde8f3df..d43fd624a6 100644
--- a/src/arch/mips/include/arch/cpu.h
+++ b/src/arch/mips/include/arch/cpu.h
@@ -110,10 +110,20 @@ do {									\
 
 
 #define C0_ENTRYLO_PFN_SHIFT 6
-#define C0_ENTRYLO_WB (0x3 << 3) /* Cacheable, write-back, non-coherent */
-#define C0_ENTRYLO_D (0x1 << 2) /* Writeable */
-#define C0_ENTRYLO_V (0x1 << 1) /* Valid */
-#define C0_ENTRYLO_G (0x1 << 0) /* Global */
+
+#define C0_ENTRYLO_COHERENCY_MASK	0x00000038
+#define C0_ENTRYLO_COHERENCY_SHIFT	3
+/* Cacheable, write-back, non-coherent */
+#define C0_ENTRYLO_COHERENCY_WB		(0x3 << C0_ENTRYLO_COHERENCY_SHIFT)
+/* Uncached, non-coherent */
+#define C0_ENTRYLO_COHERENCY_UC		(0x2 << C0_ENTRYLO_COHERENCY_SHIFT)
+
+/* Writeable */
+#define C0_ENTRYLO_D			(0x1 << 2)
+/* Valid */
+#define C0_ENTRYLO_V			(0x1 << 1)
+/* Global */
+#define C0_ENTRYLO_G			(0x1 << 0)
 
 #define C0_PAGEMASK_SHIFT 13
 #define C0_PAGEMASK_MASK 0xffff
diff --git a/src/arch/mips/include/arch/mmu.h b/src/arch/mips/include/arch/mmu.h
index ab17fec61e..8997e27f44 100644
--- a/src/arch/mips/include/arch/mmu.h
+++ b/src/arch/mips/include/arch/mmu.h
@@ -50,6 +50,6 @@ static inline uint32_t get_tlb_size(void)
 	return tlbsize;
 }
 
-int identity_map(uint32_t start, size_t len);
+int identity_map(uint32_t start, size_t len, uint32_t coherency);
 
 #endif /* __MIPS_ARCH_MMU_H */
diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c
index 38f496deb3..b144fd3573 100644
--- a/src/arch/mips/mmu.c
+++ b/src/arch/mips/mmu.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/cpu.h>
 #include <arch/mmu.h>
 #include <console/console.h>
 #include <stddef.h>
@@ -70,22 +69,23 @@ static uint32_t pick_pagesize(uint32_t start, uint32_t len)
  * Identity map the memory from [start,start+len] in the TLB using the
  * largest suitable page size so as to conserve TLB entries.
  */
-int identity_map(uint32_t start, size_t len)
+int identity_map(uint32_t start, size_t len, uint32_t coherency)
 {
 	uint32_t pgsize, pfn, entryhi, entrylo0, entrylo1;
 
+	coherency &= C0_ENTRYLO_COHERENCY_MASK;
 	while (len > 0) {
 		pgsize = pick_pagesize(start, len);
 		entryhi = start;
 		pfn = start >> 12;
-		entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | C0_ENTRYLO_WB |
+		entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | coherency |
 			C0_ENTRYLO_D | C0_ENTRYLO_V | C0_ENTRYLO_G;
 		start += pgsize;
 		len -= MIN(len, pgsize);
 		if (len >= pgsize) {
 			pfn = start >> 12;
 			entrylo1 = (pfn << C0_ENTRYLO_PFN_SHIFT) |
-				C0_ENTRYLO_WB | C0_ENTRYLO_D | C0_ENTRYLO_V |
+				coherency | C0_ENTRYLO_D | C0_ENTRYLO_V |
 				C0_ENTRYLO_G;
 			start += pgsize;
 			len -= MIN(len, pgsize);
diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c
index 5d38278942..eceb814447 100644
--- a/src/soc/imgtec/pistachio/bootblock.c
+++ b/src/soc/imgtec/pistachio/bootblock.c
@@ -54,7 +54,7 @@ static void bootblock_mmu_init(void)
 		dram_base += null_guard_size;
 		dram_size -= null_guard_size;
 	}
-
-	assert(!identity_map(dram_base, dram_size));
-	assert(!identity_map((uint32_t)_sram, _sram_size));
+	assert(!identity_map((uint32_t)_sram, _sram_size,
+						C0_ENTRYLO_COHERENCY_WB));
+	assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB));
 }