diff options
| author | Furquan Shaikh <furquan@google.com> | 2016-06-01 15:09:21 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-03 04:53:58 +0200 |
| commit | e3a692d7daf16d53764a4b0e30531491d4ae24bd (patch) | |
| tree | bedb6cd4b275ddc21d64926f36009a7cf6c150bf /src | |
| parent | b54a2d1d76549fc6dfacb880439d8785a50a589f (diff) | |
intel/apollolake: Clear TSEG reg early in bootblock
TSEG register comes out of reset with a non-zero default value. This
causes issues when cbmem_top returns non-zero value based on TSEG read
before DRAM is initialized. Thus, clear TSEG reg early in bootblock to
avoid unwanted side-effects.
Change-Id: Id3c6c270774108e4caf56e2a07c5072edc65bb58
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15049
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index b8d6f22e7a..68ce7ab640 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -60,6 +60,12 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo) /* Set PCI Express BAR */ pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); + /* + * Clear TSEG register - TSEG register comes out of reset with a + * non-zero default value. Clear this register to ensure that there are + * no surprises in CBMEM handling. + */ + pci_write_config32(dev, TSEG, 0); dev = P2SB_DEV; /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */ |