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authorT Michael Turney <quic_mturney@quicinc.com>2022-01-20 11:41:59 -0800
committerShelley Chen <shchen@google.com>2022-02-15 02:36:59 +0000
commitdf81e07c37fe50ef225ddf2fa5c94c2e2ada013f (patch)
treede947deef7de0dd4493e1b66096ca5873862f63e /src
parentd43e688ed2fe94ed429658ced02764527af8cb0f (diff)
herobrine: update SPI-NOR config options
Configuration support for 4k-byte addressing mode BUG=b:215605946 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> Signed-off-by: T Michael Turney <quic_mturney@quicinc.com> Change-Id: If82de6204446251dded1b83684677e6eb536e6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/herobrine/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig
index c6dfaaba84..ac3be6f1eb 100644
--- a/src/mainboard/google/herobrine/Kconfig
+++ b/src/mainboard/google/herobrine/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_QUALCOMM_SC7280
select SPI_FLASH
select SPI_FLASH_WINBOND
+ select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE
select SPI_FLASH_MACRONIX
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_SPI_TPM_CR50 if BOARD_GOOGLE_PIGLIN