diff options
| author | Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> | 2021-01-29 14:28:42 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-03 08:54:41 +0000 |
| commit | df7d4fc297dce7ac0e60777a4521b1e051ebf58f (patch) | |
| tree | 34b3613c2e7a9f11d09651fe4bf4337075da379c /src | |
| parent | a70ebdf289caf76cde5571ad34fed32a5595b260 (diff) | |
mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
Add the TBT PCIE rp setting to on and also fixes system hang
in recovery screen after selected "Power off" item problem.
BUG=b:177963941
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
build Pass
And check the system can power off normally in recovery page
Cq-Depend: chrome-internal:3581043
Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50103
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/volteer/variants/drobit/overridetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index 96c109fbb5..8ce98de848 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -60,6 +60,14 @@ chip soc/intel/tigerlake }" device domain 0 on + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end + + device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN3 + end + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" |