diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-29 07:01:10 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-01 00:53:20 +0000 |
| commit | de374e5028e06b689d3b413533bfbe63fe0ff5d6 (patch) | |
| tree | 86bdbde8b01d11deda76399dcdcbdd1644601a2c /src | |
| parent | 7266c5ec84b49db9e6f2b83fdfb51db2a87ec222 (diff) | |
drivers/intel/fsp1_1/romstage.c: Remove MCU update
On Braswell this is done in the bootblock before C code is executed.
Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/drivers/intel/fsp1_1/romstage.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index ff0380565a..62b112a3be 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -103,10 +103,6 @@ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih) timestamp_add_now(TS_START_ROMSTAGE); - /* Load microcode before RAM init */ - if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) - intel_update_microcode_from_cbfs(); - /* Display parameters */ if (!CONFIG(NO_MMCONF_SUPPORT)) printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", |