soc/intel/broadwell: Move `pei_data` out of romstage.c

Prepare to confine all `pei_data` references in raminit.c and refcode.c
so that mainboards don't need to know about its existence.

Change-Id: I55793fa274f8100643855466b6cca486896fb2c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55801
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 39 insertions, 36 deletions

diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index a18f4a6539..95af4d98a2 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -8,14 +8,12 @@
 void mainboard_fill_spd_data(struct pei_data *pei_data);
 void mainboard_post_raminit(const int s3resume);
 
-void sdram_initialize(struct pei_data *pei_data);
-void save_mrc_data(struct pei_data *pei_data);
-void setup_sdram_meminfo(struct pei_data *pei_data);
-
 struct chipset_power_state;
 struct chipset_power_state *fill_power_state(void);
 void report_platform_info(void);
 
+void perform_raminit(const struct chipset_power_state *const power_state);
+
 void systemagent_early_init(void);
 void pch_early_init(void);
 
diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c
index 9db34befff..28b3f37ed9 100644
--- a/src/soc/intel/broadwell/raminit.c
+++ b/src/soc/intel/broadwell/raminit.c
@@ -15,8 +15,9 @@
 #include <soc/pm.h>
 #include <soc/romstage.h>
 #include <soc/systemagent.h>
+#include <timestamp.h>
 
-void save_mrc_data(struct pei_data *pei_data)
+static void save_mrc_data(struct pei_data *pei_data)
 {
 	printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
 	       pei_data->data_to_save_size);
@@ -80,7 +81,7 @@ static void report_memory_config(void)
 /*
  * Find PEI executable in coreboot filesystem and execute it.
  */
-void sdram_initialize(struct pei_data *pei_data)
+static void sdram_initialize(struct pei_data *pei_data)
 {
 	size_t mrc_size;
 	pei_wrapper_entry_t entry;
@@ -137,7 +138,7 @@ void sdram_initialize(struct pei_data *pei_data)
 	report_memory_config();
 }
 
-void setup_sdram_meminfo(struct pei_data *pei_data)
+static void setup_sdram_meminfo(struct pei_data *pei_data)
 {
 	struct memory_info *mem_info;
 
@@ -175,3 +176,35 @@ void setup_sdram_meminfo(struct pei_data *pei_data)
 		dimm->bus_width = pei_dimm->bus_width;
 	}
 }
+
+void perform_raminit(const struct chipset_power_state *const power_state)
+{
+	const int s3resume = power_state->prev_sleep_state == ACPI_S3;
+
+	struct pei_data pei_data = { 0 };
+
+	mainboard_fill_pei_data(&pei_data);
+	mainboard_fill_spd_data(&pei_data);
+
+	post_code(0x32);
+
+	timestamp_add_now(TS_BEFORE_INITRAM);
+
+	pei_data.boot_mode = power_state->prev_sleep_state;
+
+	/* Initialize RAM */
+	sdram_initialize(&pei_data);
+
+	timestamp_add_now(TS_AFTER_INITRAM);
+
+	int cbmem_was_initted = !cbmem_recovery(s3resume);
+	if (s3resume && !cbmem_was_initted) {
+		/* Failed S3 resume, reset to come up cleanly */
+		printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
+		system_reset();
+	}
+
+	save_mrc_data(&pei_data);
+
+	setup_sdram_meminfo(&pei_data);
+}
diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c
index 08895f80d0..af8d30fb09 100644
--- a/src/soc/intel/broadwell/romstage.c
+++ b/src/soc/intel/broadwell/romstage.c
@@ -9,13 +9,10 @@
 #include <elog.h>
 #include <romstage_handoff.h>
 #include <soc/me.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <stdint.h>
-#include <timestamp.h>
 
 __weak void mainboard_fill_spd_data(struct pei_data *pei_data)
 {
@@ -28,8 +25,6 @@ __weak void mainboard_post_raminit(const int s3resume)
 /* Entry from cpu/intel/car/romstage.c. */
 void mainboard_romstage_entry(void)
 {
-	struct pei_data pei_data = { 0 };
-
 	post_code(0x30);
 
 	/* System Agent Early Initialization */
@@ -61,30 +56,7 @@ void mainboard_romstage_entry(void)
 	intel_me_hsio_version(&power_state->hsio_version,
 			      &power_state->hsio_checksum);
 
-	mainboard_fill_pei_data(&pei_data);
-	mainboard_fill_spd_data(&pei_data);
-
-	post_code(0x32);
-
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	pei_data.boot_mode = power_state->prev_sleep_state;
-
-	/* Initialize RAM */
-	sdram_initialize(&pei_data);
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-
-	int cbmem_was_initted = !cbmem_recovery(s3resume);
-	if (s3resume && !cbmem_was_initted) {
-		/* Failed S3 resume, reset to come up cleanly */
-		printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
-		system_reset();
-	}
-
-	save_mrc_data(&pei_data);
-
-	setup_sdram_meminfo(&pei_data);
+	perform_raminit(power_state);
 
 	romstage_handoff_init(s3resume);