diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 04:18:47 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-24 14:23:19 +0000 |
| commit | d91e20f19be7a434c9b1672eb42fae76d1fce4be (patch) | |
| tree | 441df73569c0ff390af66cc22cb58a228e0f925c /src | |
| parent | 842ee24340e1c643701ba04f11620dc7152a091b (diff) | |
skl mainboards/dt: Drop SataSalpSupport setting if disabled
The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: Icb41f0a9baded01267410bd4c9458ab4bfb82b70
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83175
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Diffstat (limited to 'src')
16 files changed, 0 insertions, 16 deletions
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index f0588da850..bb896aab2c 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -58,7 +58,6 @@ chip soc/intel/skylake device ref thermal on end device ref heci1 on end device ref sata on - register "SataSalpSupport" = "0" # Ports register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 62a5ac225b..ec8a289684 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "gen3_dec" = "0x00fc0901" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 3a11a84eba..d64a9f9102 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -65,7 +65,6 @@ chip soc/intel/skylake register "s0ix_enable" = true # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 789d49a474..995ed134f3 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -35,7 +35,6 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index e661f3ac84..7817efd190 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -43,7 +43,6 @@ chip soc/intel/skylake register "CmdTriStateDis" = "1" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 5f8b4593a5..0fc683d791 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "s0ix_enable" = true # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index ea753bf737..2bb5e112c8 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -40,7 +40,6 @@ chip soc/intel/skylake register "s0ix_enable" = true # FSP Configuration - register "SataSalpSupport" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index aebec9ff6e..02c832ce68 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -40,7 +40,6 @@ chip soc/intel/skylake register "s0ix_enable" = true # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index a5db866707..fe6c1cbb68 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "CmdTriStateDis" = "1" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 786354e696..4e291ac606 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -43,7 +43,6 @@ chip soc/intel/skylake register "CmdTriStateDis" = "1" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index d274e15be1..641c5ca520 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -40,7 +40,6 @@ chip soc/intel/skylake register "s0ix_enable" = true # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 6725a913ca..2cb674f486 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -33,7 +33,6 @@ chip soc/intel/skylake register "dptf_enable" = "0" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable" = "{ [0] = 1, [1] = 1, diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 6ce7aa4560..2b3955cac6 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -28,7 +28,6 @@ chip soc/intel/skylake register "tcc_offset" = "5" # TCC of 95C # FSP Configuration - register "SataSalpSupport" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index be5b6c08b7..20e204d83d 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "dptf_enable" = "0" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "0" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 8694838632..34ef3848c4 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -22,7 +22,6 @@ chip soc/intel/skylake register "dptf_enable" = "0" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable" = "{ [0] = 0, [1] = 0, diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index d89157c629..38578e06be 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -128,7 +128,6 @@ chip soc/intel/skylake end device ref thermal on end device ref sata on - register "SataSalpSupport" = "0" register "SataSpeedLimit" = "2" register "SataPortsEnable" = "{ [0] = 1, |