Add Lenovo ThinkPad T60

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

27 files changed, 2393 insertions, 0 deletions

diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index da10e4e2ef..a08a5cc6e9 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -11,9 +11,14 @@ config BOARD_LENOVO_X60
 
 	    ThinkPad X60s (Model 1703)
 
+config BOARD_LENOVO_T60
+	bool "ThinkPad T60 / T60p"
+	help
+
 endchoice
 
 source "src/mainboard/lenovo/x60/Kconfig"
+source "src/mainboard/lenovo/t60/Kconfig"
 
 config MAINBOARD_VENDOR
 	string
diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig
new file mode 100644
index 0000000000..294384b735
--- /dev/null
+++ b/src/mainboard/lenovo/t60/Kconfig
@@ -0,0 +1,59 @@
+if BOARD_LENOVO_T60
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_CORE
+	select CPU_INTEL_SOCKET_MFCPGA478
+	select NORTHBRIDGE_INTEL_I945GM
+	select SOUTHBRIDGE_INTEL_I82801GX
+	select SUPERIO_NSC_PC87382
+	select SUPERIO_NSC_PC87384
+	select SOUTHBRIDGE_TI_PCI1X2X
+	select EC_LENOVO_PMH7
+	select EC_LENOVO_H8
+	select BOARD_HAS_FADT
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select MMCONF_SUPPORT
+	select GFXUMA
+	select BOARD_ROMSIZE_KB_2048
+	select CHANNEL_XOR_RANDOMIZATION
+	select HAVE_SMI_HANDLER
+	select HAVE_ACPI_TABLES
+	select HAVE_ACPI_RESUME
+	select TINY_BOOTBLOCK
+config MAINBOARD_DIR
+	string
+	default lenovo/t60
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffdf8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "ThinkPad T60 / T60p"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 2
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+
+endif
diff --git a/src/mainboard/lenovo/t60/Makefile.inc b/src/mainboard/lenovo/t60/Makefile.inc
new file mode 100644
index 0000000000..75152586f8
--- /dev/null
+++ b/src/mainboard/lenovo/t60/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c dock.c
+romstage-y += dock.c
diff --git a/src/mainboard/lenovo/t60/acpi/dock.asl b/src/mainboard/lenovo/t60/acpi/dock.asl
new file mode 100644
index 0000000000..ae9d19e405
--- /dev/null
+++ b/src/mainboard/lenovo/t60/acpi/dock.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "smi.h"
+
+Scope (\_SB)
+{
+	OperationRegion (DLPC, SystemIO, 0x164c, 1)
+	Field(DLPC, ByteAcc, NoLock, Preserve)
+	{
+		    ,	3,
+		DSTA,	1,
+	}
+
+	Device(DOCK)
+	{
+		Name(_HID, "ACPI0003")
+		Name(_UID, 0x00)
+		Name(_PCL, Package() { \_SB } )
+
+		Method(_DCK, 1, NotSerialized)
+		{
+			if (Arg0) {
+			   Sleep(250)
+			   /* connect dock */
+			   TRAP(SMI_DOCK_CONNECT)
+			} else {
+			   /* disconnect dock */
+			   TRAP(SMI_DOCK_DISCONNECT)
+			}
+
+			Xor(Arg0, DSTA, Local0)
+			Return (Local0)
+		}
+
+		Method(_STA, 0, NotSerialized)
+		{
+			Return (DSTA)
+		}
+	}
+}
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+	OperationRegion(PMH7, SystemIO, 0x15e0, 0x10)
+	Field(PMH7, ByteAcc, NoLock, Preserve)
+	{
+		Offset(0x0c),
+			PIDX, 8,
+		Offset(0x0e),
+			PDAT, 8,
+	}
+
+	IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x61),
+			DPWR, 1,
+	}
+
+	Method(_Q18, 0, NotSerialized)
+	{
+	       Notify(\_SB.DOCK, 3)
+	}
+
+	Method(_Q37, 0, NotSerialized)
+	{
+		if (DPWR) {
+			Notify(\_SB.DOCK, 0)
+		} else {
+			Notify(\_SB.DOCK, 3)
+		}
+	}
+}
diff --git a/src/mainboard/lenovo/t60/acpi/ec.asl b/src/mainboard/lenovo/t60/acpi/ec.asl
new file mode 100644
index 0000000000..c3569e8c41
--- /dev/null
+++ b/src/mainboard/lenovo/t60/acpi/ec.asl
@@ -0,0 +1 @@
+#include <ec/lenovo/h8/acpi/ec.asl>
diff --git a/src/mainboard/lenovo/t60/acpi/gpe.asl b/src/mainboard/lenovo/t60/acpi/gpe.asl
new file mode 100644
index 0000000000..2355a4007f
--- /dev/null
+++ b/src/mainboard/lenovo/t60/acpi/gpe.asl
@@ -0,0 +1,9 @@
+#include "smi.h"
+Scope (\_GPE)
+{
+	Method(_L18, 0, NotSerialized)
+	{
+		/* Read EC register to clear wake status */
+		Store(\_SB.PCI0.LPCB.EC.WAKE, Local0)
+	}
+}
diff --git a/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl
new file mode 100644
index 0000000000..e834ae1da9
--- /dev/null
+++ b/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
+			Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
+			Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge
+			Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge
+			Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge
+			Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge
+			Package() { 0x001dffff, 0, 0, 0x10 }, // USB
+			Package() { 0x001dffff, 1, 0, 0x11 }, // USB
+			Package() { 0x001dffff, 2, 0, 0x12 }, // USB
+			Package() { 0x001dffff, 3, 0, 0x13 }, // USB
+			Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
+			Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
+			Package() { 0x001fffff, 2, 0, 0x10 }  // SATA
+		})
+	} Else {
+		Return (Package() {
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
+			Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
+			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
+			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
+			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }  // SATA
+		})
+	}
+}
diff --git a/src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000000..548996c54c
--- /dev/null
+++ b/src/mainboard/lenovo/t60/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
+		Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+		Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+		Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
+		Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 },
+		Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x16 },
+		Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }
+	})
+ } Else {
+	Return (Package() {
+		Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 },
+		Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKB, 0x00 },
+		Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 },
+		Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 },
+		Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 },
+		Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }
+	})
+}
diff --git a/src/mainboard/lenovo/t60/acpi/mainboard.asl b/src/mainboard/lenovo/t60/acpi/mainboard.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/lenovo/t60/acpi/mainboard.asl
diff --git a/src/mainboard/lenovo/t60/acpi/platform.asl b/src/mainboard/lenovo/t60/acpi/platform.asl
new file mode 100644
index 0000000000..85a987bae0
--- /dev/null
+++ b/src/mainboard/lenovo/t60/acpi/platform.asl
@@ -0,0 +1,205 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* These come from the dynamically created CPU SSDT */
+External(PDC0)
+External(PDC1)
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	\_SB.PCI0.LPCB.EC.MUTE(1)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	// CPU specific part
+
+	// Notify PCI Express slots in case a card
+	// was inserted while a sleep state was active.
+
+	// Are we going to S3?
+	If (LEqual(Arg0, 3)) {
+		// ..
+	}
+
+	// Are we going to S4?
+	If (LEqual(Arg0, 4)) {
+		// ..
+	}
+
+	// TODO: Windows XP SP2 P-State restore
+
+	Return(Package(){0,0})
+}
+
+// Power notification
+
+External (\_PR_.CPU0, DeviceObj)
+External (\_PR_.CPU1, DeviceObj)
+
+Method (PNOT)
+{
+	If (MPEN) {
+		If(And(PDC0, 0x08)) {
+			Notify (\_PR_.CPU0, 0x80)	 // _PPC
+
+			If (And(PDC0, 0x10)) {
+				Sleep(100)
+				Notify(\_PR_.CPU0, 0x81) // _CST
+			}
+		}
+
+		If(And(PDC1, 0x08)) {
+			Notify (\_PR_.CPU1, 0x80)	 // _PPC
+			If (And(PDC1, 0x10)) {
+				Sleep(100)
+				Notify(\_PR_.CPU1, 0x81) // _CST
+			}
+		}
+
+	} Else { // UP
+		Notify (\_PR_.CPU0, 0x80)
+		Sleep(0x64)
+		Notify(\_PR_.CPU0, 0x81)
+	}
+
+	// Notify the Batteries
+	Notify(\_SB.PCI0.LPCB.EC.BAT0, 0x80) // Execute BAT1 _BST
+	Notify(\_SB.PCI0.LPCB.EC.BAT1, 0x80) // Execute BAT2 _BST
+}
+
+/* System Bus */
+
+Scope(\_SB)
+{
+	/* This method is placed on the top level, so we can make sure it's the
+	 * first executed _INI method.
+	 */
+	Method(_INI, 0)
+	{
+		/* The DTS data in NVS is probably not up to date.
+		 * Update temperature values and make sure AP thermal
+		 * interrupts can happen
+		 */
+
+		// TRAP(71) // TODO
+
+		/* Determine the Operating System and save the value in OSYS.
+		 * We have to do this in order to be able to work around
+		 * certain windows bugs.
+		 *
+		 *    OSYS value | Operating System
+		 *    -----------+------------------
+		 *       2000    | Windows 2000
+		 *       2001    | Windows XP(+SP1)
+		 *       2002    | Windows XP SP2
+		 *       2006    | Windows Vista
+		 *       ????    | Windows 7
+		 */
+
+		/* Let's assume we're running at least Windows 2000 */
+		Store (2000, OSYS)
+
+		If (CondRefOf(_OSI, Local0)) {
+			/* Linux answers _OSI with "True" for a couple of
+			 * Windows version queries. But unlike Windows it
+			 * needs a Video repost, so let's determine whether
+			 * we're running Linux.
+			 */
+
+			If (_OSI("Linux")) {
+				Store (1, LINX)
+			}
+
+			If (_OSI("Windows 2001")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP1")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP2")) {
+				Store (2002, OSYS)
+			}
+
+			If (_OSI("Windows 2006")) {
+				Store (2006, OSYS)
+			}
+		}
+
+		/* And the OS workarounds start right after we know what we're
+		 * running: Windows XP SP1 needs to have C-State coordination
+		 * enabled in SMM.
+		 */
+		If (LAnd(LEqual(OSYS, 2001), MPEN)) {
+			// TRAP(61) // TODO
+		}
+
+		/* SMM power state and C4-on-C3 settings need to be updated */
+		// TRAP(43) // TODO
+	}
+}
+
diff --git a/src/mainboard/lenovo/t60/acpi/superio.asl b/src/mainboard/lenovo/t60/acpi/superio.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/lenovo/t60/acpi/superio.asl
diff --git a/src/mainboard/lenovo/t60/acpi/video.asl b/src/mainboard/lenovo/t60/acpi/video.asl
new file mode 100644
index 0000000000..c2f9dfb459
--- /dev/null
+++ b/src/mainboard/lenovo/t60/acpi/video.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (DSPC)
+{
+	Name (_ADR, 0x00020001)
+	OperationRegion (DSPC, PCI_Config, 0x00, 0x100)
+	Field (DSPC, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0xf4),
+		       BRTC, 8
+	}
+
+	Method(BRTD, 0, NotSerialized)
+	{
+		Store(BRTC, Local0)
+		if (LGreater (Local0, 15))
+		{
+			Subtract(Local0, 16, Local0)
+			Store(Local0, BRTC)
+		}
+	}
+
+	Method(BRTU, 0, NotSerialized)
+	{
+		Store (BRTC, Local0)
+		if (LLess(Local0, 0xff))
+		{
+			Add (Local0, 16, Local0)
+			Store(Local0, BRTC)
+		}
+	}
+}
diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c
new file mode 100644
index 0000000000..d9275b5ac0
--- /dev/null
+++ b/src/mainboard/lenovo/t60/acpi_tables.c
@@ -0,0 +1,368 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "dmi.h"
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#define OLD_ACPI 0
+#if OLD_ACPI
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset (gnvs, 0, sizeof(global_nvs_t));
+
+	gnvs->LIDS = 1;
+	gnvs->PWRS = 1;
+
+	gnvs->ACTT = 0x37;
+	gnvs->PSVT = 0x4f;
+
+	gnvs->TC1V = 0x00;
+	gnvs->TC2V = 0x0a;
+	gnvs->TSPV = 0x02;
+
+	gnvs->CRTT = 0x77;
+
+	gnvs->B0SC = 0x54;
+	gnvs->APIC = 0x01;
+	gnvs->MPEN = 0x01;
+
+	gnvs->PPCM = 0x02;
+	gnvs->PCP0 = 0xbf;
+	gnvs->PCP1 = 0xbf;
+
+	gnvs->CMAP = 0x01;
+	gnvs->CMBP = 0x01;
+	gnvs->LT0  = 0x01;
+	gnvs->FDCP = 0x01;
+	gnvs->CMCP = 0x01;
+	gnvs->CMDP = 0x01;
+	gnvs->P2M  = 0x02;
+
+	gnvs->IGDS = 0x01;
+
+	gnvs->CADL = 0x09;
+	gnvs->PADL = 0x09;
+
+	gnvs->NDID = 3;
+	gnvs->DID1 = 0x80000100;
+	gnvs->DID2 = 0x80000240;
+	gnvs->DID3 = 0x80000410;
+	gnvs->DID4 = 0x80000410;
+	gnvs->DID5 = 0x00000005;
+
+	gnvs->ALAF = 0x64;
+	gnvs->LLOW = 0x2c;
+	gnvs->LHIH = 0x01;
+
+        // tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c);
+	// oemb->topm = tolud;
+}
+#endif
+
+#include "southbridge/intel/i82801gx/nvs.h"
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+
+	/* Enable both COM ports */
+	gnvs->cmap = 0x01;
+	gnvs->cmbp = 0x01;
+
+	/* IGD Displays */
+	gnvs->ndid = 3;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+}
+
+static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR  0xfed00000ULL
+	acpi_header_t *header = &(hpet->header);
+	acpi_addr_t *addr = &(hpet->addr);
+
+	memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+	/* fill out header fields */
+	memcpy(header->signature, "HPET", 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+
+	header->length = sizeof(acpi_hpet_t);
+	header->revision = 1;
+
+	/* fill out HPET address */
+	addr->space_id = 0;	/* Memory */
+	addr->bit_width = 64;
+	addr->bit_offset = 0;
+	addr->addrl = HPET_ADDR & 0xffffffff;
+	addr->addrh = HPET_ADDR >> 32;
+
+	hpet->id = 0x8086a201;	/* Intel */
+	hpet->number = 0x00;
+	hpet->min_tick = 0x0080;
+
+	header->checksum =
+	    acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* LAPIC_NMI */
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+				current, 0,
+				MP_IRQ_POLARITY_HIGH |
+				MP_IRQ_TRIGGER_EDGE, 0x01);
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+				current, 1, MP_IRQ_POLARITY_HIGH |
+				MP_IRQ_TRIGGER_EDGE, 0x01);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
+
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+	void *gnvs;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_intel_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+
+	/* Fix up global NVS region for SMI handler. The GNVS region lives
+	 * in the (high) table area. The low memory map looks like this:
+	 *
+	 * 0x00000000 - 0x000003ff	Real Mode IVT
+	 * 0x00000020 - 0x0000019c	Low MP Table (XXX conflict?)
+	 * 0x00000400 - 0x000004ff	BDA (somewhat unused)
+	 * 0x00000500 - 0x0000052f	Moved GDT
+	 * 0x00000530 - 0x00000b64	coreboot table
+	 * 0x0007c000 - 0x0007dfff	OS boot sector (unused?)
+	 * 0x0007e000 - 0x0007ffff	free to use (so no good for acpi+smi)
+	 * 0x00080000 - 0x0009fbff	usable ram
+	 * 0x0009fc00 - 0x0009ffff	EBDA (unused?)
+	 * 0x000a0000 - 0x000bffff	VGA memory
+	 * 0x000c0000 - 0x000cffff	VGA option rom
+	 * 0x000d0000 - 0x000dffff	free for other option roms?
+	 * 0x000e0000 - 0x000fffff	SeaBIOS? (conflict with low tables:)
+	 * 0x000f0000 - 0x000f03ff	PIRQ table
+	 * 0x000f0400 - 0x000f66??	ACPI tables
+	 * 0x000f66?? - 0x000f????	DMI tables
+	 */
+
+	ALIGN_CURRENT;
+
+	/* Pack GNVS into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current);
+			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_create_gnvs((global_nvs_t *)current);
+
+	/* Keep pointer around */
+	gnvs = (void *)current;
+
+	current += 0x100;
+	ALIGN_CURRENT;
+
+	/* And tell SMI about it */
+	smm_setup_structures(gnvs, NULL, NULL);
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, "COREBOOT");
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+
+	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
+	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
+#if CONFIG_WRITE_HIGH_TABLES == 1
+	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
+	current += DMI_TABLE_SIZE;
+	ALIGN_CURRENT;
+#endif
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+
+	/* Enable Dummy DCC ON# for DVI */
+	printk(BIOS_DEBUG, "Laptop handling...\n");
+	outb(inb(0x60f) & ~(1 << 5), 0x60f);
+
+	return current;
+}
diff --git a/src/mainboard/lenovo/t60/chip.h b/src/mainboard/lenovo/t60/chip.h
new file mode 100644
index 0000000000..70f9bb43a6
--- /dev/null
+++ b/src/mainboard/lenovo/t60/chip.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout
new file mode 100644
index 0000000000..3144c1e4cd
--- /dev/null
+++ b/src/mainboard/lenovo/t60/cmos.layout
@@ -0,0 +1,150 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2008 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+#409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+416        512       s       0        boot_devices
+928          8       h       0        boot_default
+936          1       e       8        cmos_defaults_loaded
+937          1       e       1        lpt
+#938         46       r       0        unused
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# ram initialization internal data
+1024         8       r       0        C0WL0REOST
+1032         8       r       0        C1WL0REOST
+1040         8       r       0        RCVENMT
+1048         4       r       0        C0DRT1
+1052         4       r       0        C1DRT1
+
+1060         1       e       1        touchpad
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+8     0     No
+8     1     Yes
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
new file mode 100644
index 0000000000..9f41a30858
--- /dev/null
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -0,0 +1,194 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+chip northbridge/intel/i945
+
+	device lapic_cluster 0 on
+		chip cpu/intel/socket_mFCPGA478
+			device lapic 0 on end
+		end
+	end
+
+	device pci_domain 0 on
+		device pci 00.0 on # Host bridge
+			subsystemid 0x17aa 0x2015
+		end
+		device pci 01.0 on # PCI-e
+			device pci 00.0 on # VGA
+				subsystemid 0x17aa 0x20a4
+			end
+		end
+
+		device pci 02.0 on # GMA Graphics controller
+			subsystemid 0x17aa 0x201a
+		end
+		device pci 02.1 on # display controller
+			subsystemid 0x17aa 0x201a
+		end
+
+		chip southbridge/intel/i82801gx
+			register "pirqa_routing" = "0x0b"
+			register "pirqb_routing" = "0x0b"
+			register "pirqc_routing" = "0x0b"
+			register "pirqd_routing" = "0x0b"
+			register "pirqe_routing" = "0x0b"
+			register "pirqf_routing" = "0x0b"
+			register "pirqg_routing" = "0x0b"
+			register "pirqh_routing" = "0x0b"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "gpi13_routing" = "2"
+			register "gpi12_routing" = "2"
+			register "gpi8_routing" = "2"
+
+			register "sata_ahci" = "0x0"
+
+			register "gpe0_en" = "0x11000006"
+
+			device pci 1b.0 on # Audio Cnotroller
+				subsystemid 0x17aa 0x2010
+			end
+			device pci 1c.0 on # Ethernet
+				subsystemid 0x17aa 0x2001
+			end
+			device pci 1c.1 on end # WLAN
+			device pci 1d.0 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.1 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.2 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.3 on # USB UHCI
+				subsystemid 0x17aa 0x200a
+			end
+			device pci 1d.7 on # USB2 EHCI
+				subsystemid 0x17aa 0x200b
+			end
+			device pci 1e.0 on # PCI Bridge
+				chip southbridge/ti/pci1x2x
+					device pci 00.0 on
+						subsystemid 0x17aa 0x2012
+					end
+					register "scr" = "0x0844d070"
+					register "mrr" = "0x01d01002"
+
+				end
+			end
+			device pci 1f.0 on # PCI-LPC bridge
+				subsystemid 0x17aa 0x2009
+				chip ec/lenovo/pmh7
+					device pnp ff.1 on # dummy
+					end
+
+					register "backlight_enable" = "0x01"
+					register "dock_event_enable" = "0x01"
+				end
+				chip ec/lenovo/h8
+					device pnp ff.2 on # dummy
+						io 0x60 = 0x62
+						io 0x62 = 0x66
+						io 0x64 = 0x1600
+						io 0x66 = 0x1604
+					end
+
+
+					register "config0" = "0xa6"
+					register "config1" = "0x05"
+					register "config2" = "0xa0"
+					register "config3" = "0x05"
+
+					register "beepmask0" = "0xfe"
+					register "beepmask1" = "0x96"
+
+					register "event2_enable" = "0xff"
+					register "event3_enable" = "0xff"
+					register "event4_enable" = "0xf4"
+					register "event5_enable" = "0x3c"
+					register "event6_enable" = "0x80"
+
+					register "wlan_enable" = "0x01"
+					register "trackpoint_enable" = "0x03"
+
+				end
+				chip superio/nsc/pc87382
+					device pnp 164e.2 on # IR
+						io 0x60 = 0x2f8
+					end
+
+					device pnp 164e.3 off # Serial Port
+						io 0x60 = 0x3f8
+					end
+
+					device pnp 164e.7 on # GPIO
+						io 0x60 = 0x1680
+					end
+
+					device pnp 164e.19 on # DLPC
+						io 0x60 = 0x164c
+					end
+				end
+
+				chip superio/nsc/pc87384
+					device pnp 2e.0 off #FDC
+					end
+
+					device pnp 2e.1 on # Parallel Port
+						io 0x60 = 0x3bc
+						irq 0x70 = 7
+					end
+
+					device pnp 2e.2 off # Serial Port / IR
+						io 0x60 = 0x2f8
+						irq 0x70 = 4
+					end
+
+					device pnp 2e.3 on # Serial Port
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+
+					device pnp 2e.7 on # GPIO
+						io 0x60 = 0x1620
+					end
+
+					device pnp 2e.a off # WDT
+					end
+				end
+			end
+			device pci 1f.1 off # IDE
+				subsystemid 0x17aa 0x200c
+			end
+			device pci 1f.2 on # SATA
+				subsystemid 0x17aa 0x200d
+			end
+			device pci 1f.3 on # SMBUS
+				subsystemid 0x17aa 0x200f
+			end
+		end
+	end
+end
diff --git a/src/mainboard/lenovo/t60/dmi.h b/src/mainboard/lenovo/t60/dmi.h
new file mode 100644
index 0000000000..96b587309d
--- /dev/null
+++ b/src/mainboard/lenovo/t60/dmi.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define DMI_TABLE_SIZE 0x55
+
+static u8 dmi_table[DMI_TABLE_SIZE] = {
+	0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
+	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
+	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
+	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
+	0x30, 0x30, 0x38, 0x00, 0x00
+};
diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c
new file mode 100644
index 0000000000..cfaead3ec5
--- /dev/null
+++ b/src/mainboard/lenovo/t60/dock.c
@@ -0,0 +1,219 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <delay.h>
+#include <arch/io.h>
+#include "dock.h"
+#include "superio/nsc/pc87384/pc87384.h"
+#include "ec/acpi/ec.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
+
+static void dlpc_write_register(int reg, int value)
+{
+	outb(reg, 0x164e);
+	outb(value, 0x164f);
+}
+
+static u8 dlpc_read_register(int reg)
+{
+	outb(reg, 0x164e);
+	return inb(0x164f);
+}
+
+static void dock_write_register(int reg, int value)
+{
+	outb(reg, 0x2e);
+	outb(value, 0x2f);
+}
+
+static u8 dock_read_register(int reg)
+{
+	outb(reg, 0x2e);
+	return inb(0x2f);
+}
+
+static void dlpc_gpio_set_mode(int port, int mode)
+{
+	dlpc_write_register(0xf0, port);
+	dlpc_write_register(0xf1, mode);
+}
+
+static void dock_gpio_set_mode(int port, int mode, int irq)
+{
+	dock_write_register(0xf0, port);
+	dock_write_register(0xf1, mode);
+	dock_write_register(0xf2, irq);
+}
+
+static void dlpc_gpio_init(void)
+{
+	/* Select GPIO module */
+	dlpc_write_register(0x07, 0x07);
+	/* GPIO Base Address 0x1680 */
+	dlpc_write_register(0x60, 0x16);
+	dlpc_write_register(0x61, 0x80);
+
+	/* Activate GPIO */
+	dlpc_write_register(0x30, 0x01);
+
+	dlpc_gpio_set_mode(0x00, 3);
+	dlpc_gpio_set_mode(0x01, 3);
+	dlpc_gpio_set_mode(0x02, 0);
+	dlpc_gpio_set_mode(0x03, 3);
+	dlpc_gpio_set_mode(0x04, 4);
+	dlpc_gpio_set_mode(0x20, 4);
+	dlpc_gpio_set_mode(0x21, 4);
+	dlpc_gpio_set_mode(0x23, 4);
+}
+
+int dlpc_init(void)
+{
+	int timeout = 1000;
+
+	/* Enable 14.318MHz CLK on CLKIN */
+	dlpc_write_register(0x29, 0xa0);
+	while(!(dlpc_read_register(0x29) & 0x10) && timeout--)
+		udelay(1000);
+
+	if (!timeout)
+		return 1;
+
+	/* Select DLPC module */
+	dlpc_write_register(0x07, 0x19);
+	/* DLPC Base Address 0x164c */
+	dlpc_write_register(0x60, 0x16);
+	dlpc_write_register(0x61, 0x4c);
+	/* Activate DLPC */
+	dlpc_write_register(0x30, 0x01);
+
+	dlpc_gpio_init();
+	return 0;
+}
+
+static int dock_superio_init(void)
+{
+	int timeout = 1000;
+	/* startup 14.318MHz Clock */
+	dock_write_register(0x29, 0xa0);
+	/* wait until clock is settled */
+	while(!(dock_read_register(0x29) & 0x10) && timeout--)
+		udelay(1000);
+
+	if (!timeout)
+		return 1;
+
+	/* set GPIO pins to Serial/Parallel Port
+	 * functions
+	 */
+	dock_write_register(0x22, 0xeb);
+
+	dock_write_register(0x07, PC87384_GPIO);
+	dock_write_register(0x60, 0x16);
+	dock_write_register(0x61, 0x20);
+
+	dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE |
+			   PC87384_GPIO_PIN_PULLUP, 0x00);
+
+	dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL |
+			   PC87384_GPIO_PIN_OE, 0x00);
+
+	dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL |
+			   PC87384_GPIO_PIN_OE, 0x00);
+
+	dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE |
+			   PC87384_GPIO_PIN_PULLUP, 0x00);
+
+	dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE |
+			   PC87384_GPIO_PIN_PULLUP, 0x00);
+
+	dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE |
+			   PC87384_GPIO_PIN_PULLUP, 0x00);
+
+	dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE |
+			   PC87384_GPIO_PIN_PULLUP, 0x00);
+
+	dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE |
+			   PC87384_GPIO_PIN_PULLUP, 0x00);
+
+	outb(0xfd, 0x1620);
+
+	/* no GPIO events enabled for PORT0 */
+	outb(0x00, 0x1622);
+	/* clear GPIO events on PORT0 */
+	outb(0xff, 0x1623);
+	outb(0xff, 0x1624);
+	/* no GPIO events enabled for PORT1 */
+	outb(0x00, 0x1626);
+
+	/* clear GPIO events on PORT1*/
+	outb(0xff, 0x1627);
+	outb(0x1F, 0x1628);
+	/* enable GPIO */
+	dock_write_register(0x30, 0x01);
+	return 0;
+}
+
+int dock_connect(void)
+{
+	int timeout = 1000;
+
+	outb(0x07, 0x164c);
+
+	timeout = 1000;
+
+	while(!(inb(0x164c) & 8) && timeout--)
+		udelay(1000);
+
+	if (!timeout) {
+		/* docking failed, disable DLPC switch */
+		outb(0x00, 0x164c);
+		dlpc_write_register(0x30, 0x00);
+		return 1;
+	}
+
+	/* Assert D_PLTRST# */
+	outb(0xfe, 0x1680);
+	udelay(1000);
+	/* Deassert D_PLTRST# */
+	outb(0xff, 0x1680);
+	udelay(10000);
+
+	return dock_superio_init();
+}
+
+void dock_disconnect(void)
+{
+	/* disconnect LPC bus */
+	outb(0x00, 0x164c);
+	/* Assert PLTRST and DLPCPD */
+	outb(0xfc, 0x1680);
+}
+
+int dock_present(void)
+{
+	outb(0x61, 0x15ec);
+	return inb(0x15ee) & 1;
+}
+
diff --git a/src/mainboard/lenovo/t60/dock.h b/src/mainboard/lenovo/t60/dock.h
new file mode 100644
index 0000000000..05c5cc4764
--- /dev/null
+++ b/src/mainboard/lenovo/t60/dock.h
@@ -0,0 +1,8 @@
+#ifndef THINKPAD_X60_DOCK_H
+#define THINKPAD_X60_DOCK_H
+
+extern int dock_connect(void);
+extern void dock_disconnect(void);
+extern int dock_present(void);
+extern int dlpc_init(void);
+#endif
diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl
new file mode 100644
index 0000000000..905c94ac67
--- /dev/null
+++ b/src/mainboard/lenovo/t60/dsdt.asl
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x03,		// DSDT revision: ACPI v3.0
+	"COREv4",	// OEM id
+	"COREBOOT",     // OEM table id
+	0x20090419	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl"
+
+	// General Purpose Events
+	#include "acpi/gpe.asl"
+
+	// mainboard specific devices
+	#include "acpi/mainboard.asl"
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include "../../../northbridge/intel/i945/acpi/i945.asl"
+			#include "../../../southbridge/intel/i82801gx/acpi/ich7.asl"
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl"
+
+	// Dock support code
+	#include "acpi/dock.asl"
+}
diff --git a/src/mainboard/lenovo/t60/fadt.c b/src/mainboard/lenovo/t60/fadt.c
new file mode 100644
index 0000000000..e45db8a351
--- /dev/null
+++ b/src/mainboard/lenovo/t60/fadt.c
@@ -0,0 +1,164 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT		0xb2
+#define   CST_CONTROL	0x85
+#define   PST_CONTROL	0x80
+#define   ACPI_DISABLE	0x1e
+#define   ACPI_ENABLE	0xe1
+#define   GNVS_UPDATE   0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, "CORE  ", 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 0x00;
+	fadt->preferred_pm_profile = PM_MOBILE;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = ACPI_ENABLE;
+	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = PST_CONTROL;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x20;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x28;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = CST_CONTROL;
+	fadt->p_lvl2_lat = 1;
+	fadt->p_lvl3_lat = 0x23;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x32;
+	fadt->iapc_boot_arch = 0x00;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
+			ACPI_FADT_DOCKING_SUPPORTED;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 0;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 0;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 0;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/lenovo/t60/irq_tables.c b/src/mainboard/lenovo/t60/irq_tables.c
new file mode 100644
index 0000000000..ee4a0d97ac
--- /dev/null
+++ b/src/mainboard/lenovo/t60/irq_tables.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * 15,		/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x1f << 3) | 0x0,	/* Interrupt router dev */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x122e,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xf5,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x02 << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA       0:02.0 */
+		{0x00, (0x1b << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio  0:1b.0 */
+		{0x00, (0x1c << 3) | 0x0, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.0 */
+		{0x00, (0x1c << 3) | 0x1, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.1 */
+		{0x00, (0x1c << 3) | 0x2, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.2 */
+		{0x00, (0x1c << 3) | 0x3, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.3 */
+		{0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.0 */
+		{0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.1 */
+		{0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.2 */
+		{0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.3 */
+		{0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI       0:1e.0 */
+		{0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC       0:1f.0 */
+		{0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE       0:1f.1 */
+		{0x00, (0x1f << 3) | 0x2, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA      0:1f.2 */
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c
new file mode 100644
index 0000000000..e6a7679e81
--- /dev/null
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <delay.h>
+#include <arch/coreboot_tables.h>
+#include "chip.h"
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <ec/lenovo/pmh7/pmh7.h>
+#include <ec/acpi/ec.h>
+#include <ec/lenovo/h8/h8.h>
+#include <northbridge/intel/i945/i945.h>
+#include <pc80/mc146818rtc.h>
+
+static void mainboard_enable(device_t dev)
+{
+	device_t dev0;
+	int touchpad;
+
+	/* enable Audio */
+	h8_set_audio_mute(0);
+
+	/* If we're resuming from suspend, blink suspend LED */
+	dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
+	if (dev0 && pci_read_config32(dev0, SKPAD) == 0xcafed00d)
+		ec_write(0x0c, 0xc7);
+
+	if (get_option(&touchpad, "touchpad") < 0)
+		touchpad = 1;
+
+	pmh7_touchpad_enable(touchpad);
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
+	.enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/lenovo/t60/mainboard_smi.c b/src/mainboard/lenovo/t60/mainboard_smi.c
new file mode 100644
index 0000000000..5e0f6a98b0
--- /dev/null
+++ b/src/mainboard/lenovo/t60/mainboard_smi.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+#include <ec/acpi/ec.h>
+#include "dock.h"
+#include "smi.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+	printk(BIOS_DEBUG, "initializing SMI\n");
+	/* Enable 0x1600/0x1600 register pair */
+	ec_set_bit(0x00, 0x05);
+	ec_set_ports(0x1604, 0x1600);
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+	static int smm_initialized;
+
+	if (!smm_initialized) {
+		mainboard_smm_init();
+		smm_initialized = 1;
+	}
+
+	switch (smif) {
+	case SMI_DOCK_CONNECT:
+		dlpc_init();
+		if (!dock_connect()) {
+			/* set dock LED to indicate status */
+			ec_write(0x0c, 0x88);
+		} else {
+			/* blink dock LED to indicate failure */
+			ec_write(0x0c, 0xc8);
+		}
+		break;
+
+	case SMI_DOCK_DISCONNECT:
+		dock_disconnect();
+		ec_write(0x0c, 0x08);
+		break;
+
+	default:
+		return 1;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0 */
+	return 0;
+}
+
diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c
new file mode 100644
index 0000000000..3181e28bc8
--- /dev/null
+++ b/src/mainboard/lenovo/t60/mptable.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <string.h>
+#include <stdint.h>
+
+static void *smp_write_config_table(void *v)
+{
+        struct mp_config_table *mc;
+	int isa_bus;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LAPIC_ADDR);
+
+        smp_write_processors(mc);
+
+	mptable_write_buses(mc, NULL, &isa_bus);
+
+	/* I/O APICs:	APIC ID	Version	State		Address */
+	smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+
+	/* Legacy Interrupts */
+	mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
+
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00);
+	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2),       0x02, 0x10);  /* PCIe root 0.02.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2),       0x02, 0x10);  /* VGA       0.02.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2),       0x02, 0x11);  /* HD Audio  0:1b.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2),       0x02, 0x14);  /* PCIe      0:1c.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe      0:1c.1 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe      0:1c.2 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe      0:1c.3 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2)       , 0x02, 0x10); /* USB       0:1d.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB       0:1d.1 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB       0:1d.2 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB       0:1d.3 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2)       , 0x02, 0x17); /* LPC       0:1f.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE       0:1f.1 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA      0:1f.2 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus   6:00.0 */
+
+	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0);
+	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1);
+
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
new file mode 100644
index 0000000000..ff26698740
--- /dev/null
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -0,0 +1,342 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <usbdebug.h>
+#include <cpu/x86/bist.h>
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
+#include "dock.h"
+
+void setup_ich7_gpios(void)
+{
+	printk(BIOS_DEBUG, " GPIOS...");
+
+	/* T60 GPIO:
+	    6: LEGACYIO#
+	    7: BDC_PRESENCE#
+	    8: H8_WAKE#
+	   10: MDI_DETECT
+	   12: H8SCI#
+	   14: CPUSB#
+	   15: CPPE#
+	   25: MDC_KILL#
+	   27: EXC_PWR_CTRL
+	   28: EXC_AUX_CTRL
+	   35: CLKREQ_SATA#
+	   36: PLANARID0
+	   37: PLANARID1
+	   38: PLANARID2
+	   39: PLANARID3
+	*/
+	outl(0x1f48f7c2, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
+	outl(0xe0e0ffc3, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
+	outl(0xfbfefb7d, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
+	/* Output Control Registers */
+	outl(0x00040000, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
+	/* Input Control Registers */
+	outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
+	outl(0x000100f0, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
+	outl(0x000000f1, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
+	outl(0x000300a3, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL2 */
+}
+
+static void ich7_enable_lpc(void)
+{
+	// Enable Serial IRQ
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	// decode range
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210);
+	// decode range
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d);
+
+	/* range 0x1600 - 0x167f */
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c);
+
+	/* range 0x15e0 - 0x10ef */
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x15e1);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c);
+
+	/* range 0x1680 - 0x169f */
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c);
+}
+
+static void early_superio_config(void)
+{
+	int timeout = 100000;
+	device_t dev = PNP_DEV(0x2e, 3);
+
+	pnp_write_config(dev, 0x29, 0xa0);
+
+	while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--)
+		udelay(1000);
+
+	/* Enable COM1 */
+	pnp_set_logical_device(dev);
+	pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
+	pnp_set_enable(dev, 1);
+}
+
+static void rcba_config(void)
+{
+	/* Set up virtual channel 0 */
+	RCBA32(0x0014) = 0x80000001;
+	RCBA32(0x001c) = 0x03128010;
+
+	/* Device 1f interrupt pin register */
+	RCBA32(0x3100) = 0x00001230;
+	RCBA32(0x3108) = 0x40004321;
+
+	/* PCIe Interrupts */
+	RCBA32(0x310c) = 0x00004321;
+	/* HD Audio Interrupt */
+	RCBA32(0x3110) = 0x00000002;
+
+	/* dev irq route register */
+	RCBA16(0x3140) = 0x1007;
+	RCBA16(0x3142) = 0x0076;
+	RCBA16(0x3144) = 0x3210;
+	RCBA16(0x3146) = 0x7654;
+	RCBA16(0x3148) = 0x0010;
+
+	/* Enable IOAPIC */
+	RCBA8(0x31ff) = 0x03;
+
+	/* Enable upper 128bytes of CMOS */
+	RCBA32(0x3400) = (1 << 2);
+
+	/* Disable unused devices */
+	RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
+	RCBA32(0x3418) |= (1 << 0); // Required.
+
+	/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
+	RCBA32(0x1e84) = 0x00020001;
+	RCBA32(0x1e80) = 0x0000fe01;
+
+	/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+	RCBA32(0x1e9c) = 0x000200f0;
+	RCBA32(0x1e98) = 0x000c0801;
+}
+
+static void early_ich7_init(void)
+{
+	uint8_t reg8;
+	uint32_t reg32;
+
+	// program secondary mlt XXX byte?
+	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+	// reset rtc power status
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+	// usb transient disconnect
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+	reg8 |= (3 << 0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+	reg32 |= (1 << 29) | (1 << 17);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+	reg32 |= (1 << 31) | (1 << 27);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+	RCBA32(0x0088) = 0x0011d000;
+	RCBA16(0x01fc) = 0x060f;
+	RCBA32(0x01f4) = 0x86000040;
+	RCBA32(0x0214) = 0x10030549;
+	RCBA32(0x0218) = 0x00020504;
+	RCBA8(0x0220) = 0xc5;
+	reg32 = RCBA32(0x3410);
+	reg32 |= (1 << 6);
+	RCBA32(0x3410) = reg32;
+	reg32 = RCBA32(0x3430);
+	reg32 &= ~(3 << 0);
+	reg32 |= (1 << 0);
+	RCBA32(0x3430) = reg32;
+	RCBA32(0x3418) |= (1 << 0);
+	RCBA16(0x0200) = 0x2008;
+	RCBA8(0x2027) = 0x0d;
+	RCBA16(0x3e08) |= (1 << 7);
+	RCBA16(0x3e48) |= (1 << 7);
+	RCBA32(0x3e0e) |= (1 << 7);
+	RCBA32(0x3e4e) |= (1 << 7);
+
+	// next step only on ich7m b0 and later:
+	reg32 = RCBA32(0x2034);
+	reg32 &= ~(0x0f << 16);
+	reg32 |= (5 << 16);
+	RCBA32(0x2034) = reg32;
+}
+
+#include <cbmem.h>
+
+void main(unsigned long bist)
+{
+	u32 reg32;
+	int boot_mode = 0;
+	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
+
+	if (bist == 0)
+		enable_lapic();
+
+	/* Force PCIRST# */
+	pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+	udelay(200 * 1000);
+	pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
+
+	ich7_enable_lpc();
+
+
+	/* dock_init initializes the DLPC switch on
+	 *  thinpad side, so this is required even
+	 *  if we're undocked.
+	 */
+	if (!dlpc_init() && dock_present()) {
+		dock_connect();
+		early_superio_config();
+		/* Set up the console */
+		uart_init();
+	}
+
+#if CONFIG_USBDEBUG
+	i82801gx_enable_usbdebug(1);
+	early_usbdebug_init();
+#endif
+
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+		outb(0x6, 0xcf9);
+		while (1) asm("hlt");
+	}
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	i945_early_initialization();
+
+	/* Read PM1_CNT */
+	reg32 = inl(DEFAULT_PMBASE + 0x04);
+	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
+	if (((reg32 >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+		boot_mode = 2;
+		/* Clear SLP_TYPE. This will break stage2 but
+		 * we care for that when we get there.
+		 */
+		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+	}
+
+	/* Enable SPD ROMs and DDR-II DRAM */
+	enable_smbus();
+
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	dump_spd_registers();
+#endif
+
+	sdram_initialize(boot_mode, spd_addrmap);
+
+	/* Perform some initialization that must run before stage2 */
+	early_ich7_init();
+
+	/* This should probably go away. Until now it is required
+	 * and mainboard specific
+	 */
+	rcba_config();
+
+	/* Chipset Errata! */
+	fixup_i945_errata();
+
+	/* Initialize the internal PCIe links before we go into stage2 */
+	i945_late_initialization();
+
+#if !CONFIG_HAVE_ACPI_RESUME
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+#if CONFIG_DEBUG_RAM_SETUP
+	sdram_dump_mchbar_registers();
+
+	{
+		/* This will not work if TSEG is in place! */
+		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+
+		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
+		ram_check(0x00000000, 0x000a0000);
+		ram_check(0x00100000, tom);
+	}
+#endif
+#endif
+#endif
+
+	MCHBAR16(SSKPD) = 0xCAFE;
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* Start address of high memory tables */
+	unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+	if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+
+		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+		 * through stage 2. We could keep stuff like stack and heap in high tables
+		 * memory completely, but that's a wonderful clean up task for another
+		 * day.
+		 */
+		if (resume_backup_memory)
+			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+	}
+#endif
+	/* Set legacy Brightness control to full brightness */
+	pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
+}
diff --git a/src/mainboard/lenovo/t60/smi.h b/src/mainboard/lenovo/t60/smi.h
new file mode 100644
index 0000000000..6eb840256a
--- /dev/null
+++ b/src/mainboard/lenovo/t60/smi.h
@@ -0,0 +1,7 @@
+#ifndef MAINBOARD_LENOVO_X60_SMI_H
+#define MAINBOARD_LENOVO_X60_SMI_H
+
+#define SMI_DOCK_CONNECT 0x01
+#define SMI_DOCK_DISCONNECT 0x02
+
+#endif