diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2024-11-14 11:09:49 +0100 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-11-19 11:51:13 +0000 |
| commit | d7846fb2ff07d3e435189e46a2d207be45245ce9 (patch) | |
| tree | 344b117b086a9d69279468c75df03ca0bb503426 /src | |
| parent | 5ca1683b324145e791350643eec389f2cd940b40 (diff) | |
soc/intel/xeon_sp: Fix VTD address
On 1st and 2nd gen Xeon-SP the VTD PCI device is not at DEVFN 0.0.
Fix the DEVFN address and thus fix an assertion in vtd_probe_bar_size().
Change-Id: Ie879e95436af92fca1fee49135938ca2b005d579
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/xeon_sp/chip_gen1.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/ioat.c | 9 |
2 files changed, 12 insertions, 3 deletions
diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index e419cc0397..0a489bc35b 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -28,6 +28,7 @@ static const STACK_RES *domain_to_stack_res(const struct device *dev) static void iio_pci_domain_read_resources(struct device *dev) { const STACK_RES *sr = domain_to_stack_res(dev); + struct device *vtd_dev; if (!sr) return; @@ -56,7 +57,10 @@ static void iio_pci_domain_read_resources(struct device *dev) sr->PciResourceMem64Base, sr->PciResourceMem64Limit + 1); /* Declare domain reserved MMIO */ - uint64_t reserved_mmio = sr->VtdBarAddress + vtd_probe_bar_size(pcidev_on_root(0, 0)); + vtd_dev = pcidev_on_root(VTD_DEV_NUM, VTD_FUNC_NUM); + assert(vtd_dev); + + uint64_t reserved_mmio = sr->VtdBarAddress + vtd_probe_bar_size(vtd_dev); if ((reserved_mmio >= sr->PciResourceMem32Base) && (reserved_mmio <= sr->PciResourceMem32Limit)) mmio_range(dev, index++, reserved_mmio, diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index fcc3a20e2d..205d915832 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -10,8 +10,8 @@ #include <intelblocks/acpi.h> #include <intelblocks/vtd.h> #include <soc/acpi.h> +#include <soc/pci_devs.h> #include <IioPcieConfigUpd.h> - #include <soc/chip_common.h> /* @@ -79,6 +79,8 @@ void create_ioat_domains(const union xeon_domain_path path, const STACK_RES *const sr, const size_t pci_segment_group) { + struct device *vtd_dev; + if (sr->BusLimit < sr->BusBase + HQM_BUS_OFFSET + HQM_RESERVED_BUS) { printk(BIOS_WARNING, "Ignoring IOAT domain with limited bus range.\n"); @@ -143,7 +145,10 @@ void create_ioat_domains(const union xeon_domain_path path, &index); /* Declare domain reserved MMIO */ - uint64_t reserved_mmio = sr->VtdBarAddress + vtd_probe_bar_size(pcidev_on_root(0, 0)); + vtd_dev = pcidev_on_root(VTD_DEV_NUM, VTD_FUNC_NUM); + assert(vtd_dev); + + uint64_t reserved_mmio = sr->VtdBarAddress + vtd_probe_bar_size(vtd_dev); if ((reserved_mmio >= sr->PciResourceMem32Base) && (reserved_mmio <= sr->PciResourceMem32Limit)) mmio_range(dev, index, reserved_mmio, |