diff options
| author | Myles Watson <mylesgw@gmail.com> | 2009-10-26 15:14:07 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-10-26 15:14:07 +0000 |
| commit | d73c1b5bf1246855a4d4e847702214a3eeb6ab82 (patch) | |
| tree | bd0cbb31eeaad93213abef425135eeaea526a823 /src | |
| parent | 074356ec819be284fb1e8d18a68678b72c5282da (diff) | |
Define some variables that were not defined. There are a couple left.
Do kbuildall then grep not.defined kbuildall.results/*
The interesting ones were GENERATE_* I had to put them in twice to make it work
correctly: once outside the menu setting the defaults, and once inside the menu.
Now they show up when they should, and are always defined
Define HAVE_INIT_TIMER to only exclude the three boards that define it to be 0
in newconfig.
Define MEM_TRAIN_SEQ to be an integer and set it correctly.
Remove CAR_FAM10 and just depend on NORTHBRIDGE_AMD_AMDFAM10
MOVNTI is a performance enhancement, and should default to 0 so it doesn't break
boards that forget to define it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
45 files changed, 186 insertions, 144 deletions
diff --git a/src/Kconfig b/src/Kconfig index 1625a0035d..b53a2daa22 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -74,10 +74,6 @@ config CPU_ADDR_BITS int default 36 -config AGP_APERTURE_SIZE - hex - default 0x0 - config XIP_ROM_BASE hex default 0xfffe0000 @@ -181,7 +177,7 @@ config HAVE_HARD_RESET config HAVE_INIT_TIMER bool - default n + default y config HAVE_MAINBOARD_RESOURCES bool @@ -189,7 +185,7 @@ config HAVE_MAINBOARD_RESOURCES config HAVE_MOVNTI bool - default y + default n config HAVE_OPTION_TABLE bool @@ -216,6 +212,7 @@ config IOAPIC default n config VIDEO_MB + default 0 int config USE_WATCHDOG_ON_BOOT @@ -230,6 +227,7 @@ config VGA config GFXUMA bool + default n help Enable Unified Memory Architecture for graphics. @@ -238,6 +236,27 @@ config GFXUMA # # endmenu +#TODO Remove this option or make it useful. +config HAVE_LOW_TABLES + bool + default y + help + This Option is unused in the code. Since two boards try to set it to + 'n', they may be broken. We either need to make the option useful or + get rid of it. The broken boards are: + asus/m2v-mx_se + supermicro/h8dme + +config HAVE_HIGH_TABLES + bool + default n + help + This variable specifies whether a given northbridge has high table + support. + It is set in northbridge/*/Kconfig. + Whether or not the high tables are actually written by coreboot is + configurable by the user via WRITE_HIGH_TABLES. + config HAVE_ACPI_TABLES bool help @@ -262,14 +281,26 @@ config HAVE_PIRQ_TABLE Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE. -config HAVE_HIGH_TABLES +#These Options are here to avoid "undefined" warnings. +#The actual selection and help texts are in the following menu. + +config GENERATE_ACPI_TABLES bool + default HAVE_ACPI_TABLES -menu "System tables" +config GENERATE_MP_TABLE + bool + default HAVE_MP_TABLE -config HAVE_LOW_TABLES +config GENERATE_PIRQ_TABLE bool - default y + default HAVE_PIRQ_TABLE + +config WRITE_HIGH_TABLES + bool + default HAVE_HIGH_TABLES + +menu "System tables" config WRITE_HIGH_TABLES bool "Write 'high' tables to avoid being overwritten in F segment" @@ -409,3 +440,16 @@ endmenu config LIFT_BSP_APIC_ID bool default n + +# These probably belong somewhere else, but they are needed somewhere. +config AP_CODE_IN_CAR + bool + default n + +config USE_INIT + bool + default n + +config ENABLE_APIC_EXT_ID + bool + default n diff --git a/src/config/Options.lb b/src/config/Options.lb index f69f94c327..4d28bd53d5 100644 --- a/src/config/Options.lb +++ b/src/config/Options.lb @@ -299,11 +299,6 @@ define CONFIG_USE_DCACHE_RAM export always comment "Use data cache as temporary RAM if possible" end -define CONFIG_CAR_FAM10 - default 0 - export always - comment "AMD family 10 CAR requires additional setup" -end define CONFIG_DCACHE_RAM_BASE default 0xc0000 format "0x%x" diff --git a/src/console/Kconfig b/src/console/Kconfig index 2e4992fec0..4aa5ed3303 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -275,3 +275,14 @@ config DEFAULT_CONSOLE_LOGLEVEL endmenu +config CONSOLE_BTEXT + bool + default n + +config CONSOLE_SROM + bool + default n + +config CONSOLE_LOGBUF + bool + default n diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 55209c57e5..fa595f94e5 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -24,7 +24,7 @@ /* leave some space for global variable to pass to RAM stage */ #define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -/* for CONFIG_CAR_FAM10 */ +/* for CAR with FAM10 */ #define CacheSizeAPStack 0x400 /* 1K */ #define MSR_FAM10 0xC001102A diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 147a56d618..5b3737123a 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -103,9 +103,6 @@ static void post_cache_as_ram(void) // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); -#ifndef CONFIG_MEM_TRAIN_SEQ -#define CONFIG_MEM_TRAIN_SEQ 0 -#endif set_sysinfo_in_ram(1); // So other core0 could start to train mem #if CONFIG_MEM_TRAIN_SEQ == 1 diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 3f80baf9e6..e1fc1a436a 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -1,6 +1,5 @@ config CPU_AMD_MODEL_10XXX bool - select HAVE_INIT_TIMER select HAVE_MOVNTI select USE_PRINTK_IN_CAR select USE_DCACHE_RAM diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 66959839c2..defbce2571 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -306,11 +306,6 @@ static void STOP_CAR_AND_CPU() stop_this_cpu(); } - -#ifndef CONFIG_MEM_TRAIN_SEQ -#define CONFIG_MEM_TRAIN_SEQ 0 -#endif - #if RAMINIT_SYSINFO == 1 static u32 init_cpus(u32 cpu_init_detectedx ,struct sys_info *sysinfo) #else @@ -478,8 +473,8 @@ static void start_node(u8 node) /* Enable routing table */ printk_debug("Start node %02x", node); -#if CONFIG_CAR_FAM10 == 1 - /* For CONFIG_CAR_FAM10 support, we need to set Dram base/limit for the new node */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 + /* For FAM10 support, we need to set Dram base/limit for the new node */ pci_write_config32(NODE_MP(node), 0x44, 0); pci_write_config32(NODE_MP(node), 0x40, 3); #endif diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index b291b646e5..e6d94151aa 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -1,6 +1,5 @@ config CPU_AMD_MODEL_FXX bool - select HAVE_INIT_TIMER select HAVE_MOVNTI select USE_PRINTK_IN_CAR select USE_DCACHE_RAM diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index a0ff1d73bc..483399c0c0 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -215,11 +215,6 @@ static void STOP_CAR_AND_CPU(void) stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... } -#ifndef CONFIG_MEM_TRAIN_SEQ -#define CONFIG_MEM_TRAIN_SEQ 0 -#endif - - #if CONFIG_MEM_TRAIN_SEQ == 1 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); #endif diff --git a/src/cpu/amd/socket_AM2r2/Config.lb b/src/cpu/amd/socket_AM2r2/Config.lb index 28d9ba9f5e..2d3d12e834 100644 --- a/src/cpu/amd/socket_AM2r2/Config.lb +++ b/src/cpu/amd/socket_AM2r2/Config.lb @@ -27,7 +27,6 @@ uses CONFIG_CPU_SOCKET_TYPE uses CONFIG_CBB uses CONFIG_CDB uses CONFIG_PCI_BUS_SEGN_BITS -uses CONFIG_CAR_FAM10 config chip.h @@ -39,8 +38,6 @@ default CONFIG_EXT_CONF_SUPPORT=0 default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG default CONFIG_CPU_SOCKET_TYPE=0x11 -default CONFIG_CAR_FAM10=1 - if CONFIG_EXT_RT_TBL_SUPPORT default CONFIG_CBB=0xff default CONFIG_CDB=0 diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig index eb67bb1b51..e9989ef4ee 100644 --- a/src/cpu/amd/socket_AM2r2/Kconfig +++ b/src/cpu/amd/socket_AM2r2/Kconfig @@ -2,7 +2,6 @@ config CPU_AMD_SOCKET_AM2R2 bool select CPU_AMD_MODEL_10XXX select HT3_SUPPORT - select CAR_FAM10 config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_F_1207/Config.lb b/src/cpu/amd/socket_F_1207/Config.lb index 5c0147af7e..447b6cbd56 100644 --- a/src/cpu/amd/socket_F_1207/Config.lb +++ b/src/cpu/amd/socket_F_1207/Config.lb @@ -27,7 +27,6 @@ uses CONFIG_CPU_SOCKET_TYPE uses CONFIG_CBB uses CONFIG_CDB uses CONFIG_PCI_BUS_SEGN_BITS -uses CONFIG_CAR_FAM10 config chip.h @@ -39,8 +38,6 @@ default CONFIG_EXT_CONF_SUPPORT=0 default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG default CONFIG_CPU_SOCKET_TYPE=0x10 -default CONFIG_CAR_FAM10=1 - if CONFIG_EXT_RT_TBL_SUPPORT default CONFIG_CBB=0xff default CONFIG_CDB=0 diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig index ae7d87a210..643827ca52 100644 --- a/src/cpu/amd/socket_F_1207/Kconfig +++ b/src/cpu/amd/socket_F_1207/Kconfig @@ -2,7 +2,6 @@ config CPU_AMD_SOCKET_F_1207 bool select CPU_AMD_MODEL_10XXX select PCI_IO_CFG_EXT - select CAR_FAM10 config CPU_SOCKET_TYPE hex diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index 3af08ec046..7804def85e 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -14,7 +14,6 @@ config BOARD_AMD_SERENGETI_CHEETAH select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select AP_CODE_IN_CAR select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT @@ -81,6 +80,11 @@ config HW_MEM_HOLE_SIZE_AUTO_INC default n depends on BOARD_AMD_SERENGETI_CHEETAH +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_AMD_SERENGETI_CHEETAH + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index ce851e8d9f..9a2ec2d2ec 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -67,6 +67,11 @@ config HW_MEM_HOLE_SIZE_AUTO_INC default n depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 +config MEM_TRAIN_SEQ + int + default 2 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb index 2d82dfde4e..35e0965fba 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb @@ -111,7 +111,6 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_AMDMCT uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_CAR_FAM10 uses CONFIG_AMD_UCODE_PATCH_FILE ### diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c index 25093fd8b1..efdc7316ea 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c @@ -49,7 +49,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -87,7 +87,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig index 1bf3635084..aa2865e11e 100644 --- a/src/mainboard/asus/a8n_e/Kconfig +++ b/src/mainboard/asus/a8n_e/Kconfig @@ -34,6 +34,11 @@ config APIC_ID_OFFSET default 0x10 depends on BOARD_ASUS_A8N_E +config MEM_TRAIN_SEQ + int + default 2 + depends on BOARD_ASUS_A8N_E + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/digitallogic/adl855pc/Kconfig b/src/mainboard/digitallogic/adl855pc/Kconfig index ff7092ca01..5a2fa333c9 100644 --- a/src/mainboard/digitallogic/adl855pc/Kconfig +++ b/src/mainboard/digitallogic/adl855pc/Kconfig @@ -24,3 +24,8 @@ config IRQ_SLOT_COUNT int default 5 depends on BOARD_DIGITALLOGIC_ADL855PC + +config HAVE_INIT_TIMER + bool + default n + depends on BOARD_DIGITALLOGIC_ADL855PC diff --git a/src/mainboard/digitallogic/msm586seg/Kconfig b/src/mainboard/digitallogic/msm586seg/Kconfig index a462c2d0e8..2f1f0b9fe6 100644 --- a/src/mainboard/digitallogic/msm586seg/Kconfig +++ b/src/mainboard/digitallogic/msm586seg/Kconfig @@ -20,3 +20,7 @@ config IRQ_SLOT_COUNT default 2 depends on BOARD_DIGITALLOGIC_MSM586SEG +config HAVE_INIT_TIMER + bool + default n + depends on BOARD_DIGITALLOGIC_MSM586SEG diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index 5f4211dd33..d151332f0c 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -12,7 +12,6 @@ config BOARD_GIGABYTE_GA_2761GXDK select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 @@ -42,6 +41,11 @@ config APIC_ID_OFFSET default 16 depends on BOARD_GIGABYTE_GA_2761GXDK +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_GIGABYTE_GA_2761GXDK + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 524fe9bde3..b9564488d9 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -14,7 +14,6 @@ config BOARD_GIGABYTE_M57SLI select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select K8_REV_F_SUPPORT @@ -45,6 +44,11 @@ config APIC_ID_OFFSET default 16 depends on BOARD_GIGABYTE_M57SLI +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_GIGABYTE_M57SLI + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index 674fd90286..f9410fd784 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -22,6 +22,11 @@ config APIC_ID_OFFSET default 0x10 depends on BOARD_MSI_MS7135 +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_MSI_MS7135 + config SB_HT_CHAIN_ON_BUS0 int default 2 @@ -52,11 +57,6 @@ config HW_MEM_HOLE_SIZEK default 0x100000 depends on BOARD_MSI_MS7135 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_MSI_MS7135 - config MAX_CPUS int default 2 @@ -67,11 +67,6 @@ config MAX_PHYSICAL_CPUS default 1 depends on BOARD_MSI_MS7135 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_MSI_MS7135 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 3e9568b0b3..997733bbf6 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -13,7 +13,6 @@ config BOARD_MSI_MS7260 select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 @@ -43,6 +42,11 @@ config APIC_ID_OFFSET default 16 depends on BOARD_MSI_MS7260 +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_MSI_MS7260 + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index 35d00a35d1..4911c576b9 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -12,7 +12,6 @@ config BOARD_MSI_MS9282 select USE_DCACHE_RAM select HAVE_HARD_RESET select IOAPIC - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 615d90794f..dbcde8b7a8 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -13,7 +13,6 @@ config BOARD_NVIDIA_L1_2PVV select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 @@ -43,6 +42,11 @@ config APIC_ID_OFFSET default 16 depends on BOARD_NVIDIA_L1_2PVV +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_NVIDIA_L1_2PVV + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index 95cef528da..74d18cfbc8 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -41,6 +41,11 @@ config APIC_ID_OFFSET default 0x10 depends on BOARD_SUPERMICRO_H8DME +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_SUPERMICRO_H8DME + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index 9d1611c593..5af3986e51 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -40,6 +40,11 @@ config APIC_ID_OFFSET default 0x10 depends on BOARD_SUPERMICRO_H8DMR +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_SUPERMICRO_H8DMR + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index 72bff0e9b4..edface050b 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -41,6 +41,11 @@ config APIC_ID_OFFSET default 0x10 depends on BOARD_SUPERMICRO_H8DMR_FAM10 +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/supermicro/h8dmr_fam10/Options.lb b/src/mainboard/supermicro/h8dmr_fam10/Options.lb index 1342e4381a..e2739a6fba 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Options.lb +++ b/src/mainboard/supermicro/h8dmr_fam10/Options.lb @@ -114,7 +114,6 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_AMDMCT uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_CAR_FAM10 uses CONFIG_AMD_UCODE_PATCH_FILE ### diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c index 121624afa8..13ae166708 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c @@ -49,7 +49,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR_FAM10 + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -88,7 +88,7 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR_FAM10 + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 92c1109005..1c8b201458 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -13,7 +13,6 @@ config BOARD_TECHNEXION_TIM8690 select USE_DCACHE_RAM select HAVE_HARD_RESET select IOAPIC - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES diff --git a/src/mainboard/tyan/s1846/Kconfig b/src/mainboard/tyan/s1846/Kconfig index 6cbf75577d..5edaefadda 100644 --- a/src/mainboard/tyan/s1846/Kconfig +++ b/src/mainboard/tyan/s1846/Kconfig @@ -43,9 +43,3 @@ config HAVE_OPTION_TABLE bool default n depends on BOARD_TYAN_S1846 - -#Override manually, as in Config.lb (FIXME) -config IRQ_SLOT_COUNT - int - default 0 - depends on BOARD_TYAN_S1846 diff --git a/src/mainboard/tyan/s2880/Kconfig b/src/mainboard/tyan/s2880/Kconfig index dc1bfb1802..6481d5ff7d 100644 --- a/src/mainboard/tyan/s2880/Kconfig +++ b/src/mainboard/tyan/s2880/Kconfig @@ -51,11 +51,6 @@ config HW_MEM_HOLE_SIZEK default 0x100000 depends on BOARD_TYAN_S2880 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2880 - config MAX_CPUS int default 4 @@ -66,11 +61,6 @@ config MAX_PHYSICAL_CPUS default 2 depends on BOARD_TYAN_S2880 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2880 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig index a5303a1398..335f1dbb99 100644 --- a/src/mainboard/tyan/s2881/Kconfig +++ b/src/mainboard/tyan/s2881/Kconfig @@ -51,11 +51,6 @@ config HW_MEM_HOLE_SIZEK default 0x100000 depends on BOARD_TYAN_S2881 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2881 - config MAX_CPUS int default 4 @@ -66,11 +61,6 @@ config MAX_PHYSICAL_CPUS default 2 depends on BOARD_TYAN_S2881 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2881 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n diff --git a/src/mainboard/tyan/s2882/Kconfig b/src/mainboard/tyan/s2882/Kconfig index 0cf1f5dc20..7de1434153 100644 --- a/src/mainboard/tyan/s2882/Kconfig +++ b/src/mainboard/tyan/s2882/Kconfig @@ -51,11 +51,6 @@ config HW_MEM_HOLE_SIZEK default 0x100000 depends on BOARD_TYAN_S2882 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2882 - config MAX_CPUS int default 4 @@ -66,11 +61,6 @@ config MAX_PHYSICAL_CPUS default 2 depends on BOARD_TYAN_S2882 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2882 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n diff --git a/src/mainboard/tyan/s2885/Kconfig b/src/mainboard/tyan/s2885/Kconfig index 2dcc218538..97fb043c0f 100644 --- a/src/mainboard/tyan/s2885/Kconfig +++ b/src/mainboard/tyan/s2885/Kconfig @@ -51,11 +51,6 @@ config HW_MEM_HOLE_SIZEK default 0x100000 depends on BOARD_TYAN_S2885 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2885 - config MAX_CPUS int default 4 @@ -66,11 +61,6 @@ config MAX_PHYSICAL_CPUS default 2 depends on BOARD_TYAN_S2885 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2885 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n diff --git a/src/mainboard/tyan/s2891/Kconfig b/src/mainboard/tyan/s2891/Kconfig index f122663fff..b891e4da10 100644 --- a/src/mainboard/tyan/s2891/Kconfig +++ b/src/mainboard/tyan/s2891/Kconfig @@ -53,11 +53,6 @@ config HW_MEM_HOLE_SIZEK default 0x100000 depends on BOARD_TYAN_S2891 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2891 - config MAX_CPUS int default 4 @@ -68,11 +63,6 @@ config MAX_PHYSICAL_CPUS default 2 depends on BOARD_TYAN_S2891 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2891 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig index 3531013782..a2181f221c 100644 --- a/src/mainboard/tyan/s2892/Kconfig +++ b/src/mainboard/tyan/s2892/Kconfig @@ -53,11 +53,6 @@ config HW_MEM_HOLE_SIZEK default 0x100000 depends on BOARD_TYAN_S2892 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2892 - config MAX_CPUS int default 4 @@ -68,11 +63,6 @@ config MAX_PHYSICAL_CPUS default 2 depends on BOARD_TYAN_S2892 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2892 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig index e04b16aad7..a99f9d3ead 100644 --- a/src/mainboard/tyan/s2895/Kconfig +++ b/src/mainboard/tyan/s2895/Kconfig @@ -53,11 +53,6 @@ config HW_MEM_HOLE_SIZEK default 0x100000 depends on BOARD_TYAN_S2895 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2895 - config MAX_CPUS int default 4 @@ -68,11 +63,6 @@ config MAX_PHYSICAL_CPUS default 2 depends on BOARD_TYAN_S2895 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2895 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 769fa9d5c0..14e5c7aa99 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -13,7 +13,6 @@ config BOARD_TYAN_S2912 select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 @@ -43,6 +42,11 @@ config APIC_ID_OFFSET default 16 depends on BOARD_TYAN_S2912 +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_TYAN_S2912 + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 80558457d5..fc6327306a 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -13,7 +13,6 @@ config BOARD_TYAN_S2912_FAM10 select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -44,6 +43,11 @@ config APIC_ID_OFFSET default 16 depends on BOARD_TYAN_S2912_FAM10 +config MEM_TRAIN_SEQ + int + default 2 + depends on BOARD_TYAN_S2912_FAM10 + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/tyan/s2912_fam10/Options.lb b/src/mainboard/tyan/s2912_fam10/Options.lb index 29e4f136e7..0a73728ef5 100644 --- a/src/mainboard/tyan/s2912_fam10/Options.lb +++ b/src/mainboard/tyan/s2912_fam10/Options.lb @@ -114,7 +114,6 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_AMDMCT uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_CAR_FAM10 uses CONFIG_AMD_UCODE_PATCH_FILE ### diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index b8b334514b..aa344c646e 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -21,11 +21,35 @@ config NORTHBRIDGE_AMD_AMDFAM10 bool select HAVE_HIGH_TABLES select HYPERTRANSPORT_PLUGIN_SUPPORT - select HT3_SUPPORT config AGP_APERTURE_SIZE hex default 0x4000000 depends on NORTHBRIDGE_AMD_AMDFAM10 +config HT3_SUPPORT + bool + default y + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config AMDMCT + bool + default y + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config MEM_TRAIN_SEQ + int + default 0 + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on NORTHBRIDGE_AMD_AMDFAM10 + source src/northbridge/amd/amdfam10/root_complex/Kconfig diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 1337a11d0b..97b1cb7622 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -32,4 +32,19 @@ config K8_HT_FREQ_1G_SUPPORT default n depends on NORTHBRIDGE_AMD_AMDK8 +config MEM_TRAIN_SEQ + int + default 0 + depends on NORTHBRIDGE_AMD_AMDK8 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on NORTHBRIDGE_AMD_AMDK8 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on NORTHBRIDGE_AMD_AMDK8 + source src/northbridge/amd/amdk8/root_complex/Kconfig |