diff options
| author | Casper Chang <casper_chang@wistron.corp-partner.google.com> | 2021-11-15 18:05:18 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-17 14:32:48 +0000 |
| commit | d16a085110d42e28d273e94f96b60ef39c4bb0c2 (patch) | |
| tree | 590573def09a2a6175cdee4699b144e3a0f3e9ad /src | |
| parent | 5c3d12eaeeb76a56c7634f700674e89fc360e007 (diff) | |
mb/google/brya/variants/primus: Correct SSD power sequence
SSD sometimes can't be detected in in warm/cold boot stress.
M.2 spec describes SSD_PERST# should be sequenced after power enable.
BUG=b:199967106
TEST=SSD was always discovered in warm/cold boot stress.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/primus/gpio.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index a324fa3454..df0930c42f 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -78,6 +78,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ @@ -117,16 +119,13 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, PLTRST), - /* B4 : PROC_GP3 ==> SSD_PERST_L - * SSD_PERST_L is released after EN_PP3300_SSD is asserted; the - * power rails take some time to come up. - */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), }; static const struct pad_config romstage_gpio_table[] = { /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_F21, 1, DEEP), }; |