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authorHannah Williams <hannah.williams@intel.com>2018-01-04 11:57:14 -0800
committerMartin Roth <martinroth@google.com>2018-01-17 17:07:51 +0000
commitcdecc0db4becbe47927b649e410fd2d0b58d1531 (patch)
tree35443db726d32b9c3884905b8b5082a5426f1855 /src
parent71053a9f396a7c861c0223bf2c6608df3bec2663 (diff)
soc/intel/apollolake: Fix prev_sleep_state on G3 exit
If waking up from S5, then prev_sleep_state was correct but not when waking up from G3. Change-Id: I39011a0846f042d224a7cd65f736e749acc8ec75 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23221 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/pmutil.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 162290ac17..dbaed70ca3 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -186,6 +186,17 @@ void soc_fill_power_state(struct chipset_power_state *ps)
ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
}
+/* Return 0, 3, or 5 to indicate the previous sleep state. */
+int soc_prev_sleep_state(const struct chipset_power_state *ps,
+ int prev_sleep_state)
+{
+ /* WAK_STS bit will not be set when waking from G3 state */
+
+ if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon1 & COLD_BOOT_STS))
+ prev_sleep_state = ACPI_S5;
+ return prev_sleep_state;
+}
+
void enable_pm_timer_emulation(void)
{
/* ACPI PM timer emulation */