diff options
| author | Martin Roth <gaumless@gmail.com> | 2023-04-19 13:37:40 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-21 15:25:41 +0000 |
| commit | c9ce5f6ec8f60cfd56eca127680032b3c6ed38de (patch) | |
| tree | 27671e8b7ab7303ca927c7a356af1a968fcbb411 /src | |
| parent | 0cca0176d59073b592a26c56e494e9bc2a903e5b (diff) | |
soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off
When one of the General-Purpose PCIe bridges is not used, it doesn't
show up on the PCI bus at all, so coreboot notes it as an issue in the
devicetree. This happens even if the device is marked as off.
To solve this, we're marking the GPP bridge devices in devicetree as
hidden, so they'll only show up in devicetree if they're actually used
on a mainboard.
BUG=None
TEST=Don't see the "PCI: Leftover static devices:" warning for these in
the boot console.
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I517776e4dedc70e957a0c836ab3c2e5d49e156d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74526
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/mendocino/chipset_mendocino.cb | 8 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/chipset_rembrandt.cb | 12 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index b4efdf593e..c1da13cd3a 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -10,10 +10,10 @@ chip soc/amd/mendocino device pci 01.0 on end # Dummy Host Bridge device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_0 hidden ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 hidden ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 hidden ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 hidden ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index 2ecb240543..fe97cf8f7d 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -10,12 +10,12 @@ chip soc/amd/mendocino device pci 01.0 on end # Dummy Host Bridge device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_0 hidden ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 hidden ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 hidden ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 hidden ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_4 hidden ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_5 hidden ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A |