soc/mediatek/mt8192: Do dram fast calibration

Load params from flash and use those params to do dram fast calibration.

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I45a4fedc623aecfd000c5860e0e85175f45b8ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

6 files changed, 155 insertions, 2 deletions

diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig
index 24122048b6..1d1cf7b79e 100644
--- a/src/soc/mediatek/mt8192/Kconfig
+++ b/src/soc/mediatek/mt8192/Kconfig
@@ -15,4 +15,27 @@ config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_RETURN_FROM_VERSTAGE
 
+config DEBUG_DRAM
+	bool "Output verbose DRAM related debug messages"
+	default y
+	help
+	  This option enables additional DRAM related debug messages.
+
+config MT8192_DRAM_EMCP
+	bool
+	default y
+	help
+	  The eMCP platform should select this option to run at different DRAM
+	  frequencies.
+
+config MT8192_DRAM_DVFS
+	bool
+	default n
+	help
+	  This options enables DRAM calibration with multiple frequencies (low,
+	  medium and high) for DVFS feature.
+
+config MEMORY_TEST
+	bool
+	default y
 endif
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 533eae294d..b047ce9394 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -20,6 +20,8 @@ romstage-y += ../common/cbmem.c
 romstage-y += emi.c
 romstage-y += flash_controller.c
 romstage-y += ../common/gpio.c gpio.c
+romstage-y += ../common/mmu_operations.c
+romstage-y += memory.c dramc_param.c ../common/memory_test.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 romstage-y += ../common/timer.c
 romstage-y += ../common/uart.c
diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c
index 7b1d3c2113..9e48918f66 100644
--- a/src/soc/mediatek/mt8192/emi.c
+++ b/src/soc/mediatek/mt8192/emi.c
@@ -8,3 +8,7 @@ size_t sdram_size(void)
 
 	return dram_size;
 }
+
+void mt_set_emi(const struct dramc_data *dparam)
+{
+}
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h
index 89ff628bde..b4e982fdff 100644
--- a/src/soc/mediatek/mt8192/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h
@@ -8,7 +8,7 @@
 #include <soc/dramc_common_mt8192.h>
 
 enum {
-	DRAMC_PARAM_HEADER_VERSION = 2,
+	DRAMC_PARAM_HEADER_VERSION = 3,
 };
 
 enum DRAMC_PARAM_STATUS_CODES {
diff --git a/src/soc/mediatek/mt8192/include/soc/emi.h b/src/soc/mediatek/mt8192/include/soc/emi.h
index 0348573bd0..02a90be789 100644
--- a/src/soc/mediatek/mt8192/include/soc/emi.h
+++ b/src/soc/mediatek/mt8192/include/soc/emi.h
@@ -3,8 +3,11 @@
 #ifndef SOC_MEDIATEK_MT8192_EMI_H
 #define SOC_MEDIATEK_MT8192_EMI_H
 
-#include <types.h>
+#include <soc/dramc_param.h>
 
 size_t sdram_size(void);
+void mt_set_emi(const struct dramc_data *dparam);
+void mt_mem_init(struct dramc_param_ops *dparam_ops);
+int complex_mem_test(u8 *start, unsigned int len);
 
 #endif /* SOC_MEDIATEK_MT8192_EMI_H */
diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c
new file mode 100644
index 0000000000..b5363b0712
--- /dev/null
+++ b/src/soc/mediatek/mt8192/memory.c
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <bootmode.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <ip_checksum.h>
+#include <soc/emi.h>
+#include <symbols.h>
+
+static int mt_mem_test(const struct dramc_data *dparam)
+{
+	if (CONFIG(MEMORY_TEST)) {
+		u8 *addr = _dram;
+		const struct ddr_base_info *ddr_info = &dparam->ddr_info;
+
+		for (u8 rank = RANK_0; rank < ddr_info->support_ranks; rank++) {
+			int i = complex_mem_test(addr, 0x2000);
+
+			printk(BIOS_DEBUG, "[MEM] complex R/W mem test %s\n",
+			       (i == 0) ? "pass" : "fail");
+
+			if (i != 0) {
+				printk(BIOS_ERR, "DRAM memory test failed\n");
+				return -1;
+			}
+
+			addr += ddr_info->rank_size[rank];
+		}
+	}
+
+	return 0;
+}
+
+static u32 compute_checksum(const struct dramc_param *dparam)
+{
+	return (u32)compute_ip_checksum(&dparam->dramc_datas,
+					sizeof(dparam->dramc_datas));
+}
+
+static int dram_run_fast_calibration(const struct dramc_param *dparam)
+{
+	if (!is_valid_dramc_param(dparam)) {
+		printk(BIOS_WARNING, "Invalid DRAM calibration data from flash\n");
+		dump_param_header((void *)dparam);
+		return -1;
+	}
+
+	const u32 checksum = compute_checksum(dparam);
+	if (dparam->header.checksum != checksum) {
+		printk(BIOS_ERR,
+		       "Invalid DRAM calibration checksum from flash "
+		       "(expected: %#x, saved: %#x)\n",
+		       checksum, dparam->header.checksum);
+		return DRAMC_ERR_INVALID_CHECKSUM;
+	}
+
+	const u16 config = CONFIG(MT8192_DRAM_DVFS) ? DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS;
+	if (dparam->dramc_datas.ddr_info.config_dvfs != config) {
+		printk(BIOS_WARNING,
+		       "Incompatible config for calibration data from flash "
+		       "(expected: %#x, saved: %#x)\n",
+		       config, dparam->dramc_datas.ddr_info.config_dvfs);
+		return -1;
+	}
+
+	printk(BIOS_INFO, "DRAM calibration data valid pass\n");
+	mt_set_emi(&dparam->dramc_datas);
+	if (mt_mem_test(&dparam->dramc_datas) == 0)
+		return 0;
+
+	return DRAMC_ERR_FAST_CALIBRATION;
+}
+
+static void mem_init_set_default_config(struct dramc_param *dparam,
+	u32 ddr_geometry)
+{
+	memset(dparam, 0, sizeof(*dparam));
+
+	if (CONFIG(MT8192_DRAM_EMCP))
+		dparam->dramc_datas.ddr_info.ddr_type = DDR_TYPE_EMCP;
+
+	if (CONFIG(MT8192_DRAM_DVFS))
+		dparam->dramc_datas.ddr_info.config_dvfs = DRAMC_ENABLE_DVFS;
+	dparam->dramc_datas.ddr_info.ddr_geometry = ddr_geometry;
+
+	printk(BIOS_INFO, "DRAM-K: ddr_type: %d, config_dvfs: %d, ddr_geometry: %d\n",
+		dparam->dramc_datas.ddr_info.ddr_type,
+		dparam->dramc_datas.ddr_info.config_dvfs,
+		dparam->dramc_datas.ddr_info.ddr_geometry);
+}
+
+static void mt_mem_init_run(struct dramc_param_ops *dparam_ops, u32 ddr_geometry)
+{
+	struct dramc_param *dparam = dparam_ops->param;
+
+	/* Load calibration params from flash and run fast calibration */
+	mem_init_set_default_config(dparam, ddr_geometry);
+	if (dparam_ops->read_from_flash(dparam)) {
+		printk(BIOS_INFO, "DRAM-K: Running fast calibration\n");
+		if (dram_run_fast_calibration(dparam) != 0) {
+			printk(BIOS_ERR, "Failed to run fast calibration\n");
+
+			/* Erase flash data after fast calibration failed */
+			memset(dparam, 0xa5, sizeof(*dparam));
+			dparam_ops->write_to_flash(dparam);
+		} else {
+			printk(BIOS_INFO, "Fast calibration passed\n");
+			return;
+		}
+	} else {
+		printk(BIOS_WARNING, "Failed to read calibration data from flash\n");
+	}
+}
+
+void mt_mem_init(struct dramc_param_ops *dparam_ops)
+{
+	const struct sdram_info *sdram_param = get_sdram_config();
+
+	mt_mem_init_run(dparam_ops, sdram_param->ddr_geometry);
+}